Part Number: ADS6142
I am using the ADS6142 in an application where I have an event that is synchronized with the ADC input clock so that I expect consistent results in the sampled output data stream. After struggling to build an rough model of the ADC behavior and interaction with the analog front end for my FPGA test bench, I realized that the sampled data timing was not what I would expect given the relative timing of the signals. I am operating at 12MHz with a 62.5ns event, so it is fairly obvious to correlate the event behavior with the data stream, and the only conclusion I can draw from the data is that the ADC is intiating conversion on the falling edge of the ADC input clock, not the rising edge. I have tested and observed the same behavior when operating at 24MHz, and also managed to get an FPGA model that matches my actual circuit behavior if I assume a falling edge conversion. I have validated the clock polarity as well. The data sheet very clearly states the conversion happens within 2.5ns fo the rising edge. Can you please confirm that this is actually the case?
