Part Number: TLA2518
We have a system with a TLA2518 per card on a backplane.
On power-up we have slots where the TLA2518 does not behave as expected. Simple actions like driving GPIO7 does not work when multiple cards are installed. Single cards at a time work fine and examining the nCS of each device with a 2.5gsps scope we do see only one selected at any one time.
These same daughter cards work fine in other backplane slots leading us to believe the silicon is not damaged from ESD/EOS.
Scoping the signals of TLA2518 devices in working and non-working slots after slowing the SPI clock to <500khz and adding 1ms delays between nCS transitions and clock edges we do not see any improvement. SPI mode is 0 0 with clock idle low, data sampled on rising/transitions on falling edge.
To our surprise we are able to read the registers of the TLA2518 devices installed in the slots where they typically do not operate. I am able to dump the register values from an non-operating TLA2518 while it is not working.
Comparing the registers in working and non-working slots we see the following
System Status Reg working 0x81 non-working 0x80 - BOR/POR detected only on the good part
General Config Reg working 0x00 non-working 0x08 - bit 3 is reserved but the "TLA2518.h" TI published many years ago lists this bit as i2c clock stretching enabled. The TLA2518 is listed as SPI interface only making me believe the I2C functionality is imperfect.
Channel Select Reg working 0x00 non-working 0x09 - a non-existent channel as channels are 0-7 but the channel select is described as 4 bits which allows for up to 16 channels.
From these register values I have 2 questions:
- What is the min ramp rate for a valid power-on reset?
- Is there a pin strapping to enable to TLA2518 to boot with in a test mode or with an i2c interface enabled and we are inadvertently entering this mode while the rails are coming up or the bus state?
Many thanks
Jonathan
