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ADS1298 would not always start

Vladimir Grankovsky
Prodigy 40 points

Other Parts Discussed in Thread: ADS1298

Hello!

I'm new to the forums. I'm trying to communicate with my ADS1298 from PIC18F microcontroller via ADUM1402 digital isolator. Sometimes ADS1298 starts (1), sometimes doesn't (2) and sometimes it starts but works very strangely (3). I could possibly damage ADS1298 (and I don't know how to check it), because one time I've confused the polarity of DGND/DVDD (but I've noticed it in a few seconds and turned everything off)

The three modes of it's work are listed below.

1 (normal?). It starts and issues DRDY signal:

The data packets also look normal:
What I'm not sure about is if the packets are right (seems like ADS didn't get all SPI instructions).
Mode 2 (not starting). DRDY = 1 all the time.
Mode 3 (strange). The DRDY looks like that:
(or, more precisely, these pulses continually change)
Here is a part of my schematics (you need to zoom in to see the IC) http://dl.dropbox.com/u/18309787/ADC.pdf
The CS and Start inputs are tied to the ground (not shown here).
The analog supply is +(-) 2.5V
The digital supply is about 3.4 V.
The DGND is connected to the AGND.
Here is a part of my program code:

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    OpenSPI(SPI_FOSC_64, MODE_01, SMPMID);

    mLED_On();

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    var = putcSPI(0x06);                   // RESET

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    //var = putcSPI(0x06);                   // RESET (sometimes I try that)

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    Delay10KTCYx(240);                     // delay for 400 mS

    var = putcSPI(0x11); // SDATAC

    var = putcSPI(0x40 | 0x01);        // WREG from CONFIG1

    var = putcSPI(0x02);                   // 3 bytes

   var = putcSPI(0x86);                   // CONFIG1 = 86

    var = putcSPI(0x10);                   // CONFIG2 = 10

    var = putcSPI(0xE0);                   // CONFIG3 = E0

    // Channels

    var = putcSPI(0x40 | 0x05);        // WREG from CH1SET

    var = putcSPI(0x07);                   // 8 bytes

    var = putcSPI(0x05);                   // CH1SET = 05

    var = putcSPI(0x00);                   // ...

    var = putcSPI(0x00);

    var = putcSPI(0x00);

    var = putcSPI(0x00);

    var = putcSPI(0x00);

    var = putcSPI(0x05);

    var = putcSPI(0x05);

    var = putcSPI(0x08); // START

    var = putcSPI(0x10); // RDATAC

    while (DRDY);                          // wait for DRDY to go low

    mLED_Off();

I would be really thankful for any help with that.
  • 0
    TI__Guru**** 183421 points

    Hi Vladimir,

    Welcome to our forum!  The first screen shot below does look like a normal DRDY signal from the ADS1298 - without the data transfer captured as well, it's a little difficult to be 100% sure though.  If you simply start the device converting and monitor the DRDY pulse, it will look like a low going signal at the configured data rate.  Not sure how you would get into your Mode 2, where DRDY is always high unless you have the START pin held low or have somehow got the ADS1298 in a continuous state of reset.  You mode 3 could be the result of not having your SPI clock/data transfer synchronized to the DRDY impulse. 

    I don't see anything wrong in the way you are configuring the ADS1298, nor do I see anything in the schematic snippet that would cause you to have communication problems.  Can you zoom in with a screen shot on one of your configuration write cycles?  We can try to verify from that if you have the proper SPI clock to data phase relationship.  You can also simply try reading back your registers to verify that what you think you wrote is what you actually read back in return. 

  • 0 in reply to Tom Hendrick
    Prodigy 40 points

    Thank you for your reply.

    It seems like I've solved the problem. I can normally set up ADS1298 and verify registers in case if I connect it's signal inputs AFTER the controller starts up and before it sends the first SPI-command. If the signal inputs are connected at the time of the start-up of all the system, it doesn't work. Probably it's because at start-time my controller makes some output (I don't know exactly what yet) that switches the ADS1298 into some mode that does not accept any SPI commands.

    I'll provide more results when possible.

  • 0 in reply to Vladimir Grankovsky
    Prodigy 40 points

    I've made another controller PCB. Now I can control also the RESET pin of the ads1298. After the controller starts, I wait for some time, issue the RESET pulse, and configure ADS.

    After configuration I read some registers and verify, and they are actually correct.

    But the problem I'm having now is with DRDY signal. Just after I issue the SPI 'start' command, it starts being inverted: all the time low with short high pulses. DOUT signal has the same pattern. Sometimes (I've not realized when), however, it starts normally. What could cause that problem?

  • 0 in reply to Vladimir Grankovsky
    TI__Mastermind 43915 points

    Hi Vladimir,

    /DRDY falling edge indicates new data is available. The /DRDY signal will stay low until it sees a SCLK pulse. The first SCLK pulse will bring /DRDY high again. If you are running the converter and do not read data back, you will just see /DRDY appear to idle low with short high pulses when new data is ready.

    Regards,

    Tony Calabria