Part Number: ADS127L11
Other Parts Discussed in Thread: ADS127L21
If I need to sample at above 50 ksps the documentation indicates that I need to use the high speed mode that is good up to 400 ksps. However, if I need only (for example) 200 ksps, will I save power by clocking at that sample rate? In general, once I am in the high speed mode, how does power consumpation scale with sample rate?
Hello James,
Welcome to the TI E2E community.
If you need 200ksps, then you will need to use the high speed mode. However, instead of operating at 25.6MHz in high speed, you can reduce the clock to 12.8MHz and use the OSR 32 setting. The data rate for the ADS127L11 is f-CLK/(2*OSR). These settings will give you 200ksps. There will still be an increase in power from low power mode, but will be slightly less power than using high speed mode, f-CLK=25.6MHz, and OSR=64 for a 200ksps data rate.
If your application is power sensitive and you are targeting around 200ksps, you may want to use the ADS127L21. This device is pin to pin drop in for the ADS127L11, and offers additional speed modes. Using the mid-speed mode and f-CLK=12.8MHz, you can further reduce power consumption verses using the ADS127L11 in high speed mode, especially if using the low-latency filter.
ADS127L11 high speed mode power dissipation (Power will be less at 12.8MHz by about 3mW for the below conditions):
ADS127L21 mid speed mode power dissipation:
Regards,
Keith Nicholas
Precision ADC Applications
