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ADC12DJ3200:2 ADCs(4ch ) Sync

ttd
Mastermind 9335 points

Part Number: ADC12DJ3200
Other Parts Discussed in Thread: LMK04828

Dear Technical Support Team,

I'm considering a solution based on JESD204B Subclass 1, using a combination of Zynq UltraScale+ and a suitable ADC.

I'm are currently focusing on two ADC12DJ3200, which supports JESD204B and can be used in a 4-channel ADC configuration.

Our questions are:

 

Is it possible to achieve high-accuracy channel-to-channel synchronization using ADC12DJ3200?

I aim to perform ADC with multiple channels (4ch) synchronized using ACD for RF signals in the 1.5GHz band. It is necessary to synchronize the sampling timing of the multiple ADCs with high precision.

Specifically, we want to synchronize the sampling timing of each channel to within 1/4λ to 1/16λ (150ps to 37.5ps) of 1.5GHz.

I aim to minimize the difference in the “sampling instant” of the ADC input as much as possible.

 

I understand that Subclass1 achieves channel-to-channel synchronization at the tens-of-picosecond level, and that tADJ (time adjust) allows delay tuning with approximately 19 fs resolution.

Therefore, we believe that very fine alignment should be possible in theory, but we would like to confirm whether this is achievable in practice with ADC12DJ3200 in a multi-channel configuration.

Any guidance, limitations, or recommended architecture would be greatly appreciated.

Best Regards,

ttd

  • 0
    TI__Prodigy 70 points

    Hello, 

    Thank you for your question. I am working on creating a recommended block diagram and tips for you on this process. Are there any other restrictions to this configuration that I should be aware of? 

  • 0 in reply to Jessica Cye
    Mastermind 9335 points

    Hi Jessica,

    Could you please dual ADC12DJ3200 for 4ch simultaneous sanmpling as much as possible.

    I aim to minimize the difference in the “sampling instant” of the ADC input as much as possible.

    When supplying the sampling clock from LMK04828 to two ADCs, I believe it is necessary to use equal-length wiring(Length Matching ) to minimize skew and ensure the clock has low jitter.

    I

    Best Regards,

    ttd

  • 0 in reply to ttd
    Mastermind 9335 points

    Hi Jessica,

    Do you have any update so far?

    Best Regards,

    ttd

  • 0 in reply to ttd
    TI__Prodigy 70 points

    Hello, 

    It is definitely important to length match the signals when creating a board to ensure that they arrive close to the same time. It is important to note that when length matching these signals, be sure to base the matching on time delay instead of pure wire length. This will help to get the sampling instant as small as possible. 

    I also recommend looking into using tADJ in your set up. tADJ can be configured to help minimize the sampling instance as well internal of the ADC in dual-channel mode. There is more to find about tADJ in the datasheet (see picture below).

    Hope this helps!

    Sincerely,

    Jessica

  • 0 in reply to Jessica Cye
    Mastermind 9335 points

    Hi Jessica,

    Thank you for your advice.

    There is more to find about tADJ in the datasheet (see picture below).

    I can't see your attached picture.

    Could you re-post it again?

    Best Regards,

    ttd

  • 0 in reply to ttd
    TI__Prodigy 70 points

    Hello, 

    Yes, I will try to repost it again. If you are unable to see it, the descriptions can be found on page 79 of the datasheet. You can also find more information of the tADJ registers past this section of the datasheet.

    Sincerely,

    Jessica