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ADS7067: Input leakage current at analog inputs

Michael Tirel
Prodigy 30 points

Part Number: ADS7067
Other Parts Discussed in Thread: OPA325

Hi,

we use the ADS7067 in one of our applications. For the most connected analog signals we use the OPA325 as input buffer, but for some slow changing (nearly constant) signals we simply use a RC filter at the analog input. The values of the RC-filter are 10k and 100nF. In addition, there is the kickback RC filter directly at the input of the ADS. 

Measurements show that there is a voltage drop over the 10k of appx. 50mV which indicates that there is a leakage current of appx. 5uA.

Is it possible that there is a input leakage current at the analoge inputs of the ADS because I do not find something about it in the datasheet.

Before the ADS is configured by the CPU there is no leakage. Maybe there is some dynamic leakage phenomena.

Design details:

-Reference voltage of ADS7067: 5V (external REF195)

-Supply voltage: AVDD 5.2V; DVDD 1.8V

-Sample rate: 500kSamples/s

-number of used channels: 8

-mode: auto-sequence mode

-Kickback at all inputs: 180R/680pf

 

  • 0
    TI__Expert 7900 points

    Hello Michael, 

    Thank you for posting on TI's E2E Forum! 

    The ADS7067 has a low leakage multiplexer, 5uA is beyond expectations. Just to confirm, this 50mV voltage drop is seen when the ADC's internal mux in not enabled on the particular channel correct? 

    Michael Tirel said:
    Before the ADS is configured by the CPU there is no leakage

    Aside the auto sequence mode, is there any other configurations on the device?  Is the full system powered up before CPU configuration? does the CPU configuration include powering up the ADC or only communication? 

    For your nearly constant signals, where the 10k/100nF RC is placed, what is the source impedance before the RC? What is the expected voltage swing of the source? Or current sourcing capabilities?

    Best regards, 

    Yolanda

  • 0 in reply to Yolanda Gonzalez
    Prodigy 30 points

    Hi Yolanda,

     thanks for your help.

     At first, the answers to your questions:

     We do not use the CPU for power sequencing this is done in HW. I´m sure that the ADS is completely powered up when the configuration process is started.

     Yes, there are several configuration steps are performed:

     register             data              Description

    ---------------------------------------------------------------------

    0x04                  0x02             500ksps

    0x02                  0x10             append_status = 4-bit channel ID is appended to ADC data

    0x05                  0x00             set all channels to analog input

    0x12                  0xFF             all channels enabled for scanning sequence

    0x10                  0x11             seq_mode = 01b and seq_start = 1b start channel sequencing

     After every step of the config I read back the register content to be sure that the registers are correctly written

    The constant signals are supply voltages of the board which can be considered as low impedance signals.

    These voltages generated by a step down converter which have only a few mV ripple.

    I attached an oscilloscope picture (picture 1). It shows the supply monitored 3.3V supply voltage (channel 4; green); the voltage after the RC filter (channel 1; yellow) and the SPI clock which is used for configuration of the ADS (channel 2; red)

    The measurement shows that the voltage drops begins after the configuration of the ADS is performed and the cyclic sampling starts. The 3V3 supply voltage is not affected by the sampling.

     In the meantime I performed several other measurements.

    I also tried to reduce the sampling rate by reducing the spi data transfer rate. Refer picture2. It shows that there is no voltage drop visible in this case.

     After that I set the voltage level of the channel which is sampled before this channel to a similar voltage level. And it shows that the drop is significantly reduced even with regular spi data transfer rate.

    The results of both measurement lead me to fact that the effect is no leakage problem. It is simply the change / discharge behavior of the ADS, which has an internal RC filter. And is more significant if the sample rate is higher.

     I think the problem is solved. We simple redesign the circuit and use a lower resistor value for the RC filter or an external opamp.

  • 0 in reply to Michael Tirel
    TI__Expert 7900 points

    Thank you for sharing all that Michael,

    Unfortunately I was not able to see the images shared, but your description of them was very helpful. 

    I do agree that it seems to be the source not being able to drive the internal sample and hold circuit of the ADC .

    When there is no ADC driver, like an opamp, it is recommended to adjust the RC accordingly and slow down the sampling rate to ensure proper charge sharing between external and internal RCs, and input signal settling during the acquisition time. In most cases, when the fastest sample rate is needed an external driver would be highly recommended. 

    I am glad that a solution was found though! If there is anything else we can help with during this redesign please let us know! 

    Best regards, 

    Yolanda