Part Number: ADS7128
Hello!
I'm trying to bring up the ADS7128 from a host that does not support clock stretching. So far my programming sequence looks like this:
- reset IC via register write and wait for reboot
- enable statistics (register 0x01, bit 4)
- enable averaging filter (register 0x03, set to 0x01)
- select the channel to read (register 0x11, set 0x05) - for this example let's read channel 5
- initiate a conversion (register 0x01, bit 3)
- poll the osr ready bit until it's high (register 0x00, bit 3)
- Read latest ch5 lsb (register 0xAA)
- Read latest ch5 msb (register 0xAB)
With the above sequence, I'm always getting 0s back from those last two register reads. My list of questions is:
- It is unclear to me if it's possible to initiate the conversion and read from the "statistics" registers without enabling the OSR filter. Does the conversion initiation bit apply to normal conversions or just using the OSR?
- Will the 4 appended status bits and/or test code (DATA_CFG register bit 7) apply to the "statistics" registers? My guess is they don't as the osr expands to be 16 bits
- Are there other options to be able to use this ADC without clock stretching?
- If using the OSR + statistics registers is the best bet, is there anything that stands out as immediately wrong in the sequence I sent above?
I can send logic analyzer screenshots over email if it will help, but I have confirmed register reading and writing are generally working so far.
Thanks for the help,
Nick
