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ADS131M08: Internal voltage reference shift follow up

Brett Sawyers
Prodigy 10 points

Part Number: ADS131M08

I have been requested to contact through this channel instead of through support channels. 

I saw this conversation from a few years ago, but it wasn;t publicly finalised.

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1159235/ads131m08-internal-reference-voltage-shift-of-ads131m08?tisearch=e2e-sitesearch&keymatch=ADS131M08

Can you confirm or deny if any further investigations into root cause were conducted for the shift this customer saw in their tests? Our applications would be affected if there is a known failure mode that can force the internal reference voltage to shift, assuming that the digital scaling factor of the conversion circuitry in the IC is static (I'm assuming this is set once at factory, I have asked a separate technical question about this).

If there is a known root cause to this symptom, perhaps we can detect it in our application and take actions to reset the AFE if we detect the root cause has occurred in the field. 

  • 0
    TI__Mastermind 48035 points

    Hi Brett,

    I can not open the link in your post, but I guess you refer to the internal Vref on ADS131M08. Please see the explanation about the design below:

    The typical internal voltage reference value that is measured on the REFIN pin will be close to 1.18V, as shown in Figure 6-29 data sheet plots.  However, there is internal scaling applied to the reference voltage, so that the full scale input range will be +/-1.2V/gain, and this corrected voltage will have an accuracy of +/-0.1% typical and temperature drift of 8ppm/C typical as shown in the datasheet specifications.

    • When using the internal reference, the typical digital scaling factor applied is 1.2V/1.18V=1.017, but this value will vary slightly depending on the actual value of the internal reference for each device. 
    • When using the external reference option, a fixed digital scaling factor of 0.96 is applied so that a standard 1.25V external reference voltage will still result in a full scale input range of +/-1.2V/gain.

    I hope this helps to clear up your confusion.

    BR,

    Dale

  • 0 in reply to Dale Li
    Prodigy 10 points

    Good Morning.

    The original post was discussing observed error to the IC's internal VREF during and after unit level EFT and ESD tests. The OP stated that they observed a larger than 5% error on VREF sustained after completion of the tests, which required a "reboot" of their unit to fix. Not quite sure what reboot means unfortunately - soft or hard.

    Before the Test Vref During the test Vref After the test Vref After reinitialize of ADC Vref
    1.195 1.195 - 1.256 or 1.195 - 1.16 (Fluctuating) 1.256 or 1.16 1.195

    Cole Macias responded with "That's an interesting result for the test, I'll have to talk to the team if they have any suggestions." along with other observations. But there was no further public conversation on the topic.

    Have the engineering team any notes on known events that can cause this or a similar failure mode, where Vref shifts out of tolerance after certain events? We can atleast monitor for such events, where possible, and attempt a resolution to bring Vref back into tolerance without human intervention.

  • 0 in reply to Brett Sawyers
    TI__Mastermind 48035 points

    Hi Brett,

    Thank you for your clarification.

    EFT and ESD test are highly related to system design, so a proper system design especially PCB layout is more important to suppress high voltage transients and protect the ADC from the transient signals. The amplitude of those transients is as high as thousands of volts, which far exceeds the absolute maximum ratings of input signals allowed by most devices (the following tables shows the absolute maximum ratings for ADS131M08), so any devices could be affected by such transients. If your design has to pass such EFT or ESD tests or the operation environment of your product has such transients or overstress conditions, you have to consider proper protection circuits and PCB layout design. The following link shows one of the protection techniques, fyi.

    Circuit for protecting ADS131M0x ADC from electrical overstress

    BR,

    Dale

  • 0 in reply to Dale Li
    Prodigy 10 points

    The question is adjacent to the OPs testing.

    What I'm really looking for here, is if there are any engineering notes related to this device beyond the datasheet that show sustained variation in Vref after specific events. Vibe, shock, EFT, ESD, temperature shock (not the datasheet listed variations). The OP has noted one instance, are there already internal documentation of more?

    Trying not to reinvent the wheel during our own system level HALT RCA. An example - If we notice unexpected measurement drift spike during HALT, but have existing known failure modes for components in acquisition chain, pinpointing the failure element would be significantly simpler.

    If this information simply is not available even under NDA, mark this as closed.

  • 0 in reply to Brett Sawyers
    TI__Mastermind 48035 points

    Hi Brett,

    Unfortunately, there are no such documents.

    BR,

    Dale