Part Number: ADC12DJ5200-SEP
Regarding the ADC12DJ5200-SEP, we’d like to understand what the bus width is and how the sampling data is transferred from the ADC to the FPGA when using decimation by 4 and decimation by 8.
We are working in JMODE 46 and 54.
According to the datasheet:
- In JMODE 46: 8-bit I and 8-bit Q
- In JMODE 54: 16-bit I and 16-bit Q
Thanks!

