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ADS8168: Tacq duration

David Drouin
Prodigy 10 points

Part Number: ADS8168
Other Parts Discussed in Thread: TINA-TI

Hi,

I would like to know if it's possible to increase Tacq duration (300ns).

For example, by reducing the SLCK frequency or lowering the sampling rate.

I would like to know if it is possible to avoid using any AOP. Under what conditions?

 

Regards

David

  • 0
    TI__Mastermind 20980 points

    Hi David,

    Apologies for not getting back to this thread. Primary support is out on leave and the thread went unassigned. 

    Acquisition and conversion (also known as sample and hold) are the two stages of a SAR ADC's operation. In acquisition mode, the sampling switch which connects the analog input pin to the internal sampling capacitor array is closed. This fills the charge on the capacitor. 

    At the end of acquisition, the sampling switch is opened, and the input voltage is stored as charge on the sampling capacitor. 

    In most cases, the sampling switch is normally closed, in constant acquisition, and only opens when the actual analog-to-digital conversion process is initiated. Conversion time (tconv) is listed as a maximum spec, setting a ceiling on the maximum amount of time the ADC will be "busy" converting. On this device, the READY pin will go high while ~CS is also high (deasserted) to indicate the end of the conversion cycle. 

    From the timing diagram, you can see that tcycle = tconv + tacq, so if tconv is bounded to the 300ns maximum time, any remaining cycle time that is not used for conversion is returned as extra acquisition time. Increasing the time between conversion cycles and slowing down the SCLK frequency would both directly help to increase acquisition time. Let me know if that is clear!

    Regards,
    Joel

  • +1 in reply to Joel Meraz
    Prodigy 10 points

    Hi Joel,

    That answers some of my questions.
    So I can increase Tacq by increasing the time between conversion cycles. That’s clear.

    Does that actually make it possible to increase the circuit impedance at the ADC’s AINx inputs?

    For example, would doubling the time allow me to double the impedance?

    Regards,

    David

  • 0 in reply to David Drouin
    TI__Mastermind 20980 points

    Hi David, 

    That is correct, but you have to ensure you are settling within 16-bit accuracy in the first place.

    Your input impedance, assuming a first-order RC, forms an RC time constant (τ), which limits how quickly the voltage at the output of the RC circuit responds to a voltage applied at the input.

    ln(2^(n+1)) gives you the number of RC time constants necessary to settle within 1/2 LSB of an n-bit ADC, derived from the equation for the voltage across a capacitor over time in an RC circuit. This is considering a worst-case full-scale step input (e.g 0V to 5V), so it will be forgiving of changes in the input voltage smaller than a full-scale-range step. A 16-bit ADC then requires 11.78τ to settle within 1/2 LSB. You must ensure 11.78τ is less than the acquisition time, tacq.

    Simulation is usually the best way to verify the performance of the ADC input driver, which might be represented by higher order circuits in reality. For this I usually recommend watching our TI Precision Labs videos on ADCs, specifically the "Building the SAR ADC Simulation Model" video, which walks you through setting up simulation within the TINA-TI SPICE software. 

    https://www.ti.com/video/series/precision-labs/ti-precision-labs-analog-to-digital-converters-adcs.html

    Regards,
    Joel