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ADS8353: Frame delay time

Shuji Ishiwata
Mastermind 8840 points

Part Number: ADS8353

Hi All,


I have a question about ADS8353.

When communicating in 32CLK single SDO mode, 48 SCLK are required, but the SCLK transmitted from the MPU is transferred at 16-bit intervals.
16bit_16bit_16bit = 48CLK
A frame transfer delay occurs in the transfer interval between these 16-bit and 16-bit transfers. Is there any specification for this delay time?


Best Regards,
Ishiwata

  • 0
    TI__Expert 7410 points

    Hello Ishiwata, 

    There is not.   So long as the CS does not go high in between the 16-bit transfers, it should work fine.  The device counts the SCLK falling edges, so depending in the mode, if the CS remains low until the minimum required SCLK falling edges are seen by the device it should be ok to separate the transfers in smaller bursts

    Best regards, 

    Yolanda