Part Number: ADS1292
Hi Team,
Posting on behalf of our customer.
I'll share this E2E post with our customer so he can reply when needed.
We are using ADS1292RIPBS in a custom ECG design based on TIDA-01614, Figure 6 on page 8 (2-electrode implementation approach).TIDA01614 Multiparameter Front-End Reference Design for Vital Signs Patient Monitor.pdf
Hardware/setup details:
- Device: ADS1292RIPBS
- Analog supply: AVDD = 3.3V
- Digital supply: DVDD = 3.3V
- External clock: 2.048 MHz crystal (ECS2520MVLC02048BNTR)
- CLKSEL pin is held LOW (external clock mode)
- 2-electrode ECG path
- R2 and R63 are 10 MΩ (updated based on TI support recommendation)
- RLD path is implemented and enabled in our register configuration
Our startup/power sequence in firmware:
1) Set CS = HIGH, START = LOW, PWDN/RESET = HIGH, CLKSEL = LOW.
2) Delay 20 ms.
3) Pulse PWDN/RESET LOW for 10 ms, then HIGH.
4) Wait 600 ms for settling.
5) Send RESET command (0x06), delay 10 ms.
6) Send SDATAC (0x11), delay 5 ms.
7) Write configuration registers:
- CONFIG1 = 0x00
- CONFIG2 = 0xA0
- LOFF = 0x10
- CH1SET = 0x81
- CH2SET = 0x00
- RLD_SENS = 0x2C
- LOFF_SENS = 0x00
- LOFF_STAT = 0x40
- RESP1 = 0x00
- RESP2 = 0x02
8) Send RDATAC (0x10), then set START = HIGH.
Issue observed:
- VCAP2 measures around 5.2V (referenced to AVSS/GND).
- We are concerned this is abnormal.
- On chips/boards that have not undergone this full sequence, VCAP2 appears normal.
- Once a chip has gone through this power sequence, behavior remains the same across restarts.
Questions:
1) Is VCAP2 ≈ 5.2V expected for AVDD = 3.3V on ADS1292RIPBS?
2) Could this indicate a fault/damage, or is it normal charge-pump behavior?
3) Is our power-up/reset sequence valid for ADS1292RIPBS?
4) Are there strict requirements for digital pin states (CS/START/CLK/DIN/CLKSEL/PWDN) during AVDD ramp that we may be violating?
5) Could the sequence above cause latch-up or unreliable register readback?
We would appreciate recommended checks and any corrected initialization sequence.
Regards,
Danilo