DAC80004: dac8004 design review

Hi Frank,

Could the customer give more information on what the customer is seeing? Are they not seeing the DAC output, or is the DAC output incorrect?

Some notes: The DAC80004 datasheet specifies that the VREF must be less than VDD. The schematic shows VDD = 3.3V and VREF = 5V, invalidating the spec. This can cause DAC output issues. Note that the SDO pin on the DAC does not connect to the FPGA, so the FPGA cannot read back data from the device.

Thanks,
Erin

Hi Erin,

Thank you for your response.

I don't see the output on this side, I use the oscilloscope point the output pin is always about 2V, cannot form the control variable, on the graph VDD and VREF what voltage value is required to output valid?
My SDO removes the pull-down resistor, connects to a pin on the FPGA and can't read the status?
Are both VDD and VREF voltage values out of specification?

Thanks.

Best Regards,
Frank Sun
Texas Instruments Customer Support Center

Hi Frank,

With VREF being higher than VDD, there's a good chance the device is damaged. I would recommend tying VDD to 5V to avoid this issue. I assume you tied the device to 3.3V for SPI communication - If so, 3.3V SPI is functional at VDD = 5V for this device. 

Please replace the device and set it so that VDD = VREF = 5V. Please also make sure your SDI line latches on the SCLK falling edge, if it doesn't it will prevent communication.

Thanks,
Erin

Hi Erin,

I tried to set VDD to 5.12V and VREF to 5V, but the maximum output voltage at my output terminal is only 2.48V. Are there any other solutions?

Thanks.

Best Regards,
Frank Sun
Texas Instruments Customer Support Center

Hi Frank,

Good that you're seeing output now. Did you end up changing the device in case it was damaged? What value are you sending to the DAC to get fullscale output?

Thanks,
Erin

Hi Erin,

I need to send'h0000 is 0V, 'h8000 is 2.5V, 'hFFFF is 5V, I have also replaced the chip here, However, the output is the same after replacement.

Thank you.

Best Regards,
Frank Sun
Texas Instruments Customer Support Center

Hi Frank,

If you are seeing ~2.5V when you send 'hFFFF, there's a chance your SPI is not set up properly. Please check your SPI setup to ensure the data is latching on the SCLK falling edge. If you are latching on the rising edge, that could accidently force a "0" into the MSB data position, causing you to only see half-scale output at fullscale data.

Thanks,
Erin

Hi Erin,

I'm going to be on the rising edge of CLK, SCLK, I'm going to reverse it, isn't it going to be down?
Or can you help me see where my code is misconfigured?
Or is it a register configuration issue?

dac80004_spi (1).zip

Best Regards,
Frank Sun
Texas Instruments Customer Support Center