ADS7067: tD_CKDO: launch & capture edge

Hi Jonas,

I was able to test this by issuing clock transitions manually, and the advanced data launch explanation is simply not correct, and was inaccurately extrapolated from the operation of another device with "enhanced SPI", and is why we wanted to try and clarify at this point. I also would like to go back and amend these threads. Data transitions on the falling edge of SCLK, as you would expect for a peripheral set to work in SPI mode 0. 

Therefore, the td_ckdo would seemingly have the potential to cause some conflicts with reading data at 60MHz. It is highly probable that the 16ns figure was provided with excessive margin, as is common with timings to be extra safe across temperature and part-to-part variation, and was an oversight on how that would operate at full speed. The digital interface should still be fully responsive at 60MHz. I would like to preempt a question, and say that we would not be able to provide an "alternative" maximum timing to what is published in the datasheet unfortunately.

One justification I received was that, since td_ckdo is a timing characteristic of the output of the device, it doesn't directly conflict, since the device itself can still receive 60MHz as an input. I'm a little hesitant to characterize it in such a way (since ultimately this has influence on system-level considerations), but it makes sense if we only consider the device receiving SCLK, and outputting data without necessarily caring what is on the other side. 

However, through some timing analysis, it is not necessary to provide a clock frequency as high as 60MHz, but it is definitely still an option though for configuration and data readback. 

If ~CS is brought low at 220ns, that leaves 1.03us remaining in the conversion cycle to read out 16 bits of data. This equates to full throughput at a minimum SCLK frequency of 15.534 MHz. 

I hope this clarifies this a little bit more. 

Regards,
Joel