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ADS9324: SPI interface sharing and CONVST

Part Number: ADS9324

Hi,

I have 2 questions.

  1. SPI interface sharing at several devices
    1. is below connection available?
    2. FPGA has dedicated pin for CS and SDO for each devices
    3. FPGA has 2 pins for SCLK and SDI and it's shared for each devices.
  2. CONVST
    1. When CONVST is low, is data sampled at previous sampling results?
    2. after CONVST high, is data sampled at current sampling results?
    3. Customer has to get current sample so when they try to get the data, doing 2 times sampling. removed first data and get next data.
    4. if CONVST high mean giving current data, then customer would like to do 1 time sampling and with CONVST high, they would get the data.

Thanks.

  • Hello David, 

    How many devices are there planned? 

    Sharing SCLK and SDI while having individual CS and SDO should work. 

    A CONVST falling edge begins the conversion, after that the sample takes max tCONV time (1.25us) to fully convert the sample. If data is read before the tCONV is completed then the data read is a previous sample, if read after then the data is the current sample. 

    Please note that a new conversion can be started before the tconv is met, and in the next frame the initial sample will be available. 

    Best regards, 

    Yolanda 

  • HI

    This is What I inquired to David.

    I plan to share four ADS9324 devices.

    CONVST, DRDY, RESET, SDI, and SCLK will be connected to all four devices as a single net, while SDO and CS will be connected individually.

    Please let me know if there would be any issues with device control under this configuration.

  • Hi Jung,

    DRDY is the output pin of the ADC. It should not be connected together as a single net. CONVST, RESET, SDI, and SCLK can be connected together as they are inputs. I would recommend to connect at least one of the DRDY pin to your host controller. Let us know if you have any further questions.


    Regards,

    Shaury