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DAC38RF80: No DAC Output

Kenneth Falcone
Prodigy 20 points

Part Number: DAC38RF80
Other Parts Discussed in Thread: DAC38RF83

I previously had a problem with no differential outputs on a custom board using the DAC38RF83, but didn't properly bias the outputs. Rework was unable to solve the problem. I'm now working with a revised board that uses the single ended DAC38RF80 and has the same result.

ALM_SYSREF_DET reads 0x0002, which seems fine.

ALM_SD_DET reads 0x0050, which is a little weird since there are only 4 SERDES connected.

Alarm registers 0x64 to 0x6D are all zeros.

I wrote a 1 to SPI_TXENABLE in JESD_FIFO.

NCO-only mode doesn't work either. Supply voltages are within specifications.

What can cause no DAC output? I'm thinking PLL lock and power supplies, but those all seem good. It seems if the SERDES can sync, then it has to be either the digital having no output or the analog disabling the output. Is there a problem with the program?

I attached files containing the register values used to program the DAC, and those read after initialization.

Ken

DAC38RF80-260423b-single-1000x6-nco.cfg DAC38RF80-260423b.cfg 

  • 0
    TI__Guru* 82865 points

    Hello Ken,

    Would you be able to enable the internal DAC test pattern to see if you can observe an output?

    You have to enable SPIDAC_EN and then program the SPIDAC value. If you have NCO enabled, you should observe a tone at the NCO.

  • 0 in reply to Kang Hsia
    Prodigy 20 points

    I followed the instructions for NCO-only, which are in the CFG files I provided:

    0x12F = 0x0001 SPIDAC_ENA = 1

    0x130 = 0x0000 SPIDAC = 0

    0x10A = 0x8310 DAC_COMPLEMENT = 0

    I also tried other values, but still saw no output.

    Ken

  • 0 in reply to Kenneth Falcone
    TI__Guru* 82865 points

    Hi Ken,

    Could you please help me with the following?

    1. are you using PLL? If so, can you read the following PLL_LFVOLT to ensure PLL is locked?

    2. can you enable the TXENABLE GPIO? If so, could you please use SW based SPITXENABLE command?

    3. Which file is the readback value? I see the 0x04 and 0x5 registers having some alarms

    4. Your full-scale current (0x40D) is set to maximum and should already be driving at the maximum. I believe we may need to force the TXENABLE GPIO.

    5. Can you toggle SPI_SYNC? This will synchronize your NCO based on your Sync source selection. You should be able to do the following

    0x128 -> 0x0330 -> 0x0331 -> 0x0330

    0x228 -> 0x0330 -> 0x0331 -> 0x0330

    This should toggle the SPI SYNC to reset your NCOs.

  • 0 in reply to Kang Hsia
    Prodigy 20 points

    A little progress:

    PD is pulled down first
    RST_B is pulled high second
    TXENABLE pin is pulled high after writing the registers

    TEMP_PLLVOLT = 99C 4V

    ALM_SYSREF_DET reads 0x0002, which seems fine.
    ALM_SD_DET reads 0x0050, which is a little weird since there are only 4 SERDES connected.
    Alarm registers 0x64 to 0x6D are all zeros.
    I wrote a 1 to SPI_TXENABLE in JESD_FIFO.

    Toggling the SPI_SYNC made NCO only mode work, -5.8 dBm tone at 1.5 GHz.
    0x128 -> 0x0330 -> 0x0332 -> 0x0330

    Turning off SPIDAC_ENA makes the DAC output tone disappear, which I don't think should happen with input 0s and offset binary format. There is no output if I send a tone over the data either.

    Ken

  • 0 in reply to Kang Hsia
    Prodigy 20 points

    I've studied the Status Log that comes out of DAC38RFxx EVM GUI v1p1 in simulation mode to compare the order of commands, but haven't been able to make a difference. I noticed that it seems to repeat the same command several times and repeat the same pair of commands several times. Is there a reason for this that I should know about?

    It seems that when I disable SPIDAC_ENA, that the DAC is somehow disabling the output. Am I wrong in thinking that there should be an output with input 0s in offset binary format? What could be doing this?

    Ken

  • 0 in reply to Kenneth Falcone
    TI__Guru* 82865 points

    Hi Ken

    Kenneth Falcone said:
    It seems that when I disable SPIDAC_ENA, that the DAC is somehow disabling the output. Am I wrong in thinking that there should be an output with input 0s in offset binary format? What could be doing this?

    Your JESD204 link must be up and running for the input 0s with offset binary to work. If not, it is possible that the PAP is gating the input to prevent damage

    Kenneth Falcone said:
    I noticed that it seems to repeat the same command several times and repeat the same pair of commands several times. Is there a reason for this that I should know about?

    There may be synchronization commands such as synchronizing the NCOs, QMC, and divider circuits. Do you have example snippet to share?

  • 0 in reply to Kang Hsia
    Prodigy 20 points

    I'm not seeing any alarms to indicate that the JESD204 link is not up. And if there were alarms, wouldn't the JESD204 output be zeros? I haven't turned on the PAP_ENA in 0x10A MULTIDUC_CFG1.

    Repeated commands happen a lot as shown below. I tried writing the same commands without removing any repetition in the order they come out of the EVM log, but so far that makes no difference. Everything seems to work fine, but there is still no output if I turn off SPIDAC_ENA.

    Write Register: DAC38RF8x.config1[0x1] -[0x1080]
    Read Register: DAC38RF8x.config1[0x1] - [0x1080]
    Write Register: DAC38RF8x.config0[0x0] -[0x5860]
    Read Register: DAC38RF8x.config0[0x0] - [0x5860]
    Write Register: DAC38RF8x.config0[0x0] -[0x5860]
    Read Register: DAC38RF8x.config0[0x0] - [0x5860]
    Write Register: DAC38RF8x.config49[0x431] -[0x400]
    Read Register: DAC38RF8x.config49[0x431] - [0x400]
    Write Register: DAC38RF8x.config50[0x432] -[0x208]
    Read Register: DAC38RF8x.config50[0x432] - [0x208]
    Idle
    Write Register: DAC38RF8x.config51[0x433] -[0x4818]
    Read Register: DAC38RF8x.config51[0x433] - [0x4818]
    Idle
    Write Register: DAC38RF8x.config49[0x431] -[0x400]
    Read Register: DAC38RF8x.config49[0x431] - [0x400]
    Write Register: DAC38RF8x.config49[0x431] -[0x400]
    Read Register: DAC38RF8x.config49[0x431] - [0x400]
    Write Register: DAC38RF8x.config11[0x40B] -[0x2]
    Read Register: DAC38RF8x.config11[0x40B] - [0x2]
    Write Register: DAC38RF8x.config59[0x43B] -[0x0]
    Read Register: DAC38RF8x.config59[0x43B] - [0x0]
    Write Register: DAC38RF8x.config59[0x43B] -[0x0]
    Read Register: DAC38RF8x.config59[0x43B] - [0x0]
    Write Register: DAC38RF8x.config51[0x433] -[0x4818]
    Read Register: DAC38RF8x.config51[0x433] - [0x4818]
    Write Register: DAC38RF8x.config60[0x43C] -[0x8029]
    Read Register: DAC38RF8x.config60[0x43C] - [0x8029]
    Write Register: DAC38RF8x.config60[0x43C] -[0x8029]
    Read Register: DAC38RF8x.config60[0x43C] - [0x8029]
    Write Register: DAC38RF8x.config60[0x43C] -[0x8029]
    Read Register: DAC38RF8x.config60[0x43C] - [0x8029]
    Write Register: DAC38RF8x.config60[0x43C] -[0x8029]
    Read Register: DAC38RF8x.config60[0x43C] - [0x8029]
    Write Register: DAC38RF8x.config60[0x43C] -[0x8029]
    Read Register: DAC38RF8x.config60[0x43C] - [0x8029]
    Write Register: DAC38RF8x.config60[0x43C] -[0x8029]
    Read Register: DAC38RF8x.config60[0x43C] - [0x8029]

    Ken

  • 0 in reply to Kenneth Falcone
    Prodigy 20 points

    There was a problem with SYSREF. I looked at the statistics:
    SYSREF12_CNT = 0x0000
    SYSREF34_CNT = 0xFF00
    so I'm using
    SYSR_CAPTURE = 0xD800
    and I can now see SYNCB go low and go high when TXENABLE = 1.

    I powered down the SERDES transmitter.
    ALM_SD_DET is still 0x0050
    but SYNCB stays low.

    I'm now getting alarms:
    JESD_ALM_L0 = 0x0002
    JESD_ALM_L1 = 0x0002
    JESD_ALM_L2 = 0x0002
    JESD_ALM_L3 = 0x0002

    FIFO_ZEROS_DATA prevented output

    When I disable FIFO_ZEROS_DATA, the output looks pretty clean, even though I'm getting FIFO alarms.

    Is that OK?

    I changed the reference from 500 MHz to 400 MHz and I'm seeing a couple SYSREF12_CNT, and different alarms on JESD_ALM_L3.

    Ken