Part Number: ADS8900BEVM-PDK
Is the kickback filter on the board adjusted for appropriate kickback settling?
My simulation is showing a large possible settling error (Over 5 mV after 300 ns, which is the minimal acquisition time)!
The values also seem to be outside of the suggested range from your calculator:
Hi Indrit,
The analog engineer's calculator gives some rough guidance on ballpark figures that might be required from an amplifier. Most notably, gain bandwidth determines small-signal settling time. The RC filter itself is important, but is highly dependant on the specific amplifier's internal characteristics, such as compensation, output impedance, and any higher order poles they might form.
If varying the RC filter values proves unsuccessful, or the margin between proper settling time and acquisition time is not sufficient, it is likely a higher speed amplifier would be beneficial, especially when considering effects over process variation and temperature. Sometimes some amount of oscillation of the amplifier output is needed to settle within the full resolution of the ADC.
For more comprehensive guidance on designing and simulating a SAR ADC input driver, I recommend looking at our TI Precision Labs series on SAR ADC input driver design.
Regards,
Joel
