Hi all,
i use up to 6 ADS1248 on the SPI bus and want to cyclic (40 SPS) start conversions synchronized for all ADCs via START pin
I cannot observe the DRDY\ pin in my HW design, so i use the SDATAC mode to be able to readout the conversion results (always waiting until the max. conversion time (~26 ms) elapsed).
Now my question:
Is it possible to enforce a new data conversion (by a START high pulse or edge) even if a (possible running) current conversion has not finished?
Or with other words:
see the data sheet (JUNE 2011), fig. 70 (SLEEP and WAKEUP): What happens, if i start a new conversion before DRDY\ becomes low?
Actually i process as followed:
1. Power-Up (and wait > 16ms)
2. reset (by RESET\ line and wait > 0,6ms)
3. set START = 1
4. basic init all ADCs (write, readback and verify some ADC registers)
5. start SELFOCAL for all ADCs (and wait > 401 ms), readout OFC and FSC registers of all ADCs
6. setup all ADCs for measuring the first input channel
7. start (one) conversion by apply a (very short) START low-pulse (i.e. START = 1 afterwards) !!
8. wait until conversion time (~26 ms) elapsed
9. readout conversion data + setup registers for measuring the next channel, for all ADCs. -> but meanwhile the ADCs do the next conversion! -> Is this a problem or should i set START = 0 until next step??
10. start (one) conversion ... and so on (always measuring another input channel or system monitor channel)
-----
Actually all seems OK. But I'am not shure if this process is really "save", in order not to readout data from a wrong channel!?
Thanks very much,
Markus.