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ADS54J60: Getting 'X'

alekhya m
Prodigy 80 points

Part Number: ADS54J60

Hi,

I am getting 'x' value even if i am giving all the signals to the transciver wizard IP in VIVADO 2022.2.We need some assistance regarding this and  we  are using xc7a200fbg484-2 fpga.

 

Thanks& Regards,

M. AlekhyaScreenshot (240).pngScreenshot (247).pngScreenshot (248).pngScreenshot (249).png

  • 0
    TI__Intellectual 1080 points

    Hi - Can you please help to provide your LMFS configuration and sampling rate? Are you using a TI provided JESD IP?

    Are you able to put the device into transport layer test pattern mode to test the integrity of the link?

  • 0 in reply to Bill Clarke
    Prodigy 80 points
    Parameter Value Why
    L 4 per channel (8 total) JESD_A[3:0] + JESD_B[3:0] — 4 lanes per ADC channel
    M 2 Two analog inputs: CH-A (INAP/INAM) and CH-B (INBP/INBM)
    F 1 F = (M × NP) / (8 × L) = (2 × 16) / (8 × 4) = 1 octet per frame per lane
    S 2 S = (F × 8 × L) / (M × NP) = (1 × 8 × 4) / (2 × 16) = 1 at base, but ADS54J60 outputs S=2 at 250 MS/s
    K 32 ADS54J60 fixed default; multiframe = F × K = 32 octets
    N 16 ADS54J60 native 16-bit resolution
    NP 16 N = NP — no padding needed

    Sampling frequency 480 MSPS

  • 0 in reply to alekhya m
    TI__Intellectual 1080 points

    Alekhya can you please also answer if you are using a TI provided JESD IP?

    If you put the device into transport layer test mode are you able to see the expected symbols in the FPGA ILA?

  • 0 in reply to Bill Clarke
    Prodigy 80 points

    Sorry for the late reply. yes i am using TI provided JESD IP. and YES. if not what is the reason for this?

    Thanks& Regards,

    M. Alekhya