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ADC12DJ2700: TI_JESD204_IP, Loopback Simulation Issue

Part Number: ADC12DJ2700
Other Parts Discussed in Thread: TI-JESD204-IP

Hi,

I am running a loopback simulation on TI_JESD204_IP and there is a lock issue with qpll0.

I ran the simulation in two environments, GTHand GTY, and there is a problem with the lock on qpll0 in the GTY environment.

 

First, the problem-free "GTH" environment is as follows:

  1. Vivado version : 2021.2
  2. TI-JESD204-IP Reference Design : zcu102_8b10b 
  3. FPGA : kintex ultrascale, XCKU040 (GTH)
  4. Transceiver wizard's physical resource : QuadX0Y2(MGTREFCLK0) , QuadX0Y3(MGTREFCLK0 of QuadX0Y2)
  5. Results : qpll0_locked[1:0] is "11", so there is no problem. Loopback simulation is also fine.

 

Second, "GTY" environment is as follows:

  1. Vivado version : 2021.2
  2. TI-JESD204-IP Reference Design : vcu118_8b10b 
  3. FPGA : kintex ultrascale+ ,  XCKU3P(GTY)
  4. Transceiver wizard's physical resource : QuadX0Y2(MGTREFCLK0) , QuadX0Y3(MGTREFCLK0 of QuadX0Y2)
  5. Results : qpll0_locked[1:0] is "01", so the second bit does not become 1.

And the transceiver settings are the same in both environments.

transceivers setting.png

 

What could be wrong? Please help.

 

Best Regards

Cho

 

  • Hi Cho,

    Kindly confirm if the transceiver wrapper logic is identical in both cases. There is a possibility that the xcvr reference clock (gtrefclkxx_in) is not being connected correctly. It is a 2 bit input (as you are using two quads).

    Regards,
    Ameet

  • Hi Ameet Bagwe,

    I checked gty_8b10b_rxtx.sv in the TI-JESD204-IP Reference Design : vcu118_8b10b file using GTY.

    It works after changing .gtrefclk00_in (gt_refclk0_buf) -> .gtrefclk00_in ({NUM_QUADS{gt_refclk0_buf}}) in xcvr_gen.

    It seems that the NUM_QUADS parameter is missing in gtrefclk00_in in reference design vcu118_8b10b.

    It works after I modified it and ran the simulation again. 

    Best Regards,

    Cho