Part Number: ADC12DJ2700
Other Parts Discussed in Thread: TI-JESD204-IP
Hi,
I am running a loopback simulation on TI_JESD204_IP and there is a lock issue with qpll0.
I ran the simulation in two environments, GTHand GTY, and there is a problem with the lock on qpll0 in the GTY environment.
First, the problem-free "GTH" environment is as follows:
- Vivado version : 2021.2
- TI-JESD204-IP Reference Design : zcu102_8b10b
- FPGA : kintex ultrascale, XCKU040 (GTH)
- Transceiver wizard's physical resource : QuadX0Y2(MGTREFCLK0) , QuadX0Y3(MGTREFCLK0 of QuadX0Y2)
- Results : qpll0_locked[1:0] is "11", so there is no problem. Loopback simulation is also fine.
Second, "GTY" environment is as follows:
- Vivado version : 2021.2
- TI-JESD204-IP Reference Design : vcu118_8b10b
- FPGA : kintex ultrascale+ , XCKU3P(GTY)
- Transceiver wizard's physical resource : QuadX0Y2(MGTREFCLK0) , QuadX0Y3(MGTREFCLK0 of QuadX0Y2)
- Results : qpll0_locked[1:0] is "01", so the second bit does not become 1.
And the transceiver settings are the same in both environments.

What could be wrong? Please help.
Best Regards
Cho