• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 61 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC53202: Time order for VREF ramping compared with VDD

Taketo Furusawa
Intellectual 1030 points

Part Number: DAC53202

Hello team,

The VREF pin says "This pin must not ramp up before VDD.".

Are there specific orders for this timing? (ex. msec, nsec)

Best, Taketo

  • +1
    TI__Mastermind 24225 points

    Hi Taketo,

    There is no specific timing requirement. The condition exists because ramping VREF before VDD can push current though the ESD cells on the pin or cause latch-up issues. This is dependent on the voltage difference between VREF and VDD directly, so as long as VDD is maintained at a voltage level above VREF during power up and power down, you can avoid these potential problems.

    Regards,

    James