ADS5463: ADS5463 circuit needs to keep a high SNR during circuit design

This is a mechanic of high-speed ADC's. If the clock jitter is sufficiently high, this will cause large uncertainty in the sampling instant vs. the input signal which appears as noise if the input signal is also changing. In general, as the ADC input frequency approaches the sampling frequency, this error is larger and will appear as higher noise. A good rule of thumb is to keep the clock jitter below the ADC aperture jitter (the ADC's own contribution to jitter error in its sampling instant).