ADS8558: using problem

Part Number: ADS8558
Other Parts Discussed in Thread: ADS8556

Hello,

Do I need to change the hardware circuit diagram, software register configuration, and software timing to replace ADI's AD7658 with ADS8558 P2P?

Hi Allen,

Thanks for your post. The devices are P2P. The main difference is: The power-up sequence from partial power-down to normal operation is different between AD7656 and ADS8556.  For the ADS8556 another reset pulse has to be applied to wake up the device again, for the AD7658 a CONVST pulse is required.

Best regards,

Samiha

New question:

In our existing design, MCU the give ADC7658 reset signal to the pin 28 only one time during the drive initialisation.

But from the ads8558 datasheet, we can see the reset signal works during the signal transferring.

Is that what you mean "wake up the device again"?

 

  • Hello Allen, 

    What Samiha was referring to was the devices going from a partial power-down mode back to normal operation. Both devices have a functionality where any channel can be placed in partial power-down mode by setting the CONVSTx signal low before the falling edge of BUSY. To exit the partial power down mode, the AD7658 requires a CONVST pulse before it goes back into normal operation, while the ADS8556 requires a RESET pulse instead. 

    Doing a reset during initialization is a good practice, and in this aspect the initialization sequence does not need to change between both devices. 

    Best regards, 

    Yolanda

  • Hi Yolanda,

    After directly replacing AD7658 with ADS8558, channel 1 or channel 2 is connected to a DC voltage acquisition signal, and there are output values for channels 1, 2, and 4 at the same time. What could be the reason for this?

  • Hello Allen, 

    Could you please share the schematic and any configurations made on the device? is the device in serial or parallel mode? 

    When you say " channels 1, 2, and 4", do you mean CH_A1, CH_B0, CH_C0? 

    This device has 3 different CONVST for each pair of channels (A, B, C)

    In HW mode  (HW/SW = 0), a rising edge signal is needed for each CONVST to start the conversion and data output data from each channel pair.  In this mode, if all the CONVST are shorted together, this could have triggered the 3 channel data to be output.  

    In SW mode and CR bit C23 = 1 (sequential mode enabled), then similar to HW mode, a CONVST signal is needed on each CONVST, 

    if CR bit C23 = 0 (sequential mode disabled) a CONVST_A is used to start the conversion of all of the selected.

    Do you know if the device is in HW mode or SW mode? if the CR bit C23 bit is set to 0/1? or if all CONVST pins are shorted together? 

    Best regards, 

    Yolanda