Part Number: ADS8684
Hi team,
Since I haven't received a reply, I'm reposting this.
- External reference is applied to the REFIO pin.
- /REFSEL is tied to DVDD as shown in datasheet section 8.3.8.2 “External Reference” and Figure 62.
- Internal reference is disabled by /REFSEL = High.
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During power-up, when /REFSEL is tied directly to DVDD, is there any condition where the internal reference could be briefly enabled before /REFSEL is recognized as High?
In other words, is there any possibility that the internal reference output and the external reference applied to REFIO could conflict momentarily during DVDD ramp-up? -
If REFIO is driven by an external reference while AVDD = 0 V (for example, AVDD ramps after the reference is already present), is this condition supported?
- If supported, are there any constraints such as maximum injection current, required series resistance, or ramp-rate considerations?
- If not recommended, what is the preferred power-up sequencing between AVDD, DVDD, /REFSEL, and external VREF?
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If the /REFSEL pin is left floating (not connected), is its logic state defined internally?
- Does it default to internal reference or external reference mode, or is this considered an undefined condition?
Best Regards,
Ryu.