ADS127L18EVM-PDK: Understanding problem/working principle

Peter Wais

Part Number: ADS127L18EVM-PDK
Other Parts Discussed in Thread: ADS127L18

Hello,

we are using a ADS127L18EVM-PDK evalboard that we are interfacing with a stm32h753 instead of the PHI board. Our configuration settings are as follows:

GEN_CFG1 = 0x01
GEN_CFG2 = 0x04
GEN_CFG3 = 0x08
DP_CFG1 = 0x50
DP_CFG2 = 0x00
CLK_CFG = 0x00
CHx_CFG1 = 0x00
CHx_CFG2 = 0x01 (channel 0-3)
CHx_CFG2 = 0x21 (channel 4-7)

As you can see from the config we only need/use 4 channels. Hence we only have DOUT0 connected to the stm32's SAI. DOUT1 is left floating.

Our usecase is that we typically want to start conversions (via SPI command to CONTROL register) and then keep the ADC running for several minutes. During that time we stream the data via ethernet to a raspberry pi where the data is also visualized.

The START pin is connected to GND as suggested in the datasheet. As a result we are never (re)synchronizing conversions.

The problem we observe is that we always get random errors and the conversions are stopped. The errors also occur when the adc is stopped. If errors occured during stopped condition a subsequent start was ignored. Sometimes the error is visible in the STATUS register (as value 0x02). However, most of the time the STATUS register remains at 0x0. As a workaround we always clear the STATUS register when starting conversions. Now start always work, but the problem that ongoing conversions are stopped upon an error condition is still present. These errors occur independently on two separate devices in different offices.

We also made use of the GUI that is delivered with the ADS127L18EVM-PDK (with the PHI Board). We configured all the control registers to the same values as described above. Unfortunately the working principle of the PHI/GUI is completely different. Nonetheless, we tried to understand it. But we really can't.

Here are the logic analyzer results we see, when we capture 2 samples (D0-D3 are SPI; can be ignored). Single trigger on FSYNC after pressing capture button in GUI.

According to my understanding there are continuous restart conditions and also the fact that FSYNC and DCLK look nearly the same at times, doesn't make sense to me.

Even if we would not use TDM there should be 32 DCLK cycles within 1 FSYNC cycle, or? With 2 data lanes (TDM=4), there should even be 128 DCLK cycles.

Do you see an obvious problem in the way we are using the adc? Could you help us to understand the working principle of the GUI/PHI code? Any help would be highly appreciated.

Best regards,

Peter

2 months ago

0 Keith Nicholas 2 months ago

TI__Guru 51250 points

Hello Peter,

Welcome to the TI E2E community.

The ADC should work well for the settings that you are using. Using OSR=64 and the internal clock, the data rate, and FSYNC frequency, should be 200kHz. Also, there will be 128 DCLK's per FSYNC period, which will allow 4x 32b readings (8b status plus 24b conversion result).

The SPI address error should not interrupt readings. Once you start data collection, it is recommended not to read/write over the SPI port to reduce reading noise caused by the SPI SCLK. Since you are triggering the the SPI Address Error, I assume you are trying to read or write to the internal registers during data collection?

This is likely some sort of noise on the SPI port causing the SPI port to see an incorrect address. I suggest using an oscilloscope and capture a full SPI frame, including the /CS, SDI, SDO, and SCLK signals. Also confirm you are using 1.8V CMOS logic levels; the ADS127L18 does not support any other voltages on the digital pins.

The logic capture shown above appears to have a large amount of noise during the capture. The FSYNC should be a 200kHz, 50% duty cycle, for the settings you are using. DCLK should be equal to the internal oscillator frequency of 25.6MHz. I would check the logic level setting for your logic analyzer; if you have the logic analyzer set for 3.3V logic, it will result in a large amount of noise similar to what is shown. Below are two frames of captured data from the EVM, where the START pin is used to control the device.