• State TI Thinks Resolved
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 47 subscribers
  • Views 87 views
  • Users 0 members are here
Support feedback
Options
Options
Related

DAC80516: Datasheet issue and spurious AVDD_COLLAPSE

Connor Crenshaw
Prodigy 20 points

Part Number: DAC80516

I am encountering an issue where bit 3 of RESET_FLAGS (AVDD_COLLAPSE_FLAG) is always set on my DAC80516. The DAC performs normally, with percise outputs and cuccessful chip_id reads - but this flag won't go away after being cleared. During the attached scope shots of a RESET_FLAGS clear+readback, the DAC is powered with AVDD=5V, VIO=3.3V, and the reference output is a stable 2.5V that came up about a second earlier. The 5V supply is stable and low-noise and I was unable to trigger the scope off of any transients on this supply, AC or DC coupled. Is there perhpas an issue with the AVDD_COLLAPSE_FLAG implementation on this chip? Is there extra SPI or hardware configuration required for it to work correctly?

Additionally, the datasheet says the four reset flags are bits [3:0] in figure 7-16 but bits [4:1] in the first column of figure 7-17. This doesn't explain my issue, however.

Scope shots are below. Yellow is nCS, blue is SCLK, purple is MOSI, green is MISO.

Flag reset

1000040383_screen.jpg

Read command

1000040384_screen.jpg

Flag read

1000040385_screen.jpg

  • 0
    TI__Mastermind 24205 points

    Hi Connor,

    I have an evaluation module here that I can check for this behavior. I'll run a quick test to see if I have the same flag report.

    Regarding the datasheet, the bit labeling does appear to be inconsistent so I'll pass along that feedback.

    Regards,

    James

  • 0 in reply to James Steenbock
    TI__Mastermind 24205 points

    Hi Connor,

    I just checked this on the EVM and I'm also seeing the AVDD_COLLAPSE_FLAG = 1b, even though I have AVDD set to 5V and VREF sitting at 2.5V. I tried the clear multiple times to make sure and the read back 0x0008 every time which means the other flags are cleared successfully but the AVDD_COLLAPSE_FLAG is still set.

    Let me ask internally about this bit functionality to see if there's something I'm missing and report back.

    Regards,

    James

  • 0 in reply to James Steenbock
    TI__Genius 16780 points

    Hi Connor,

    I discussed this issue with design. It looks like this specific reset flag is not operating as intended, and the bit is not clearable. There is nothing wrong with your setup and VDD supply. I've made a note to update this register the next time we update the datasheet. Thank you for bringing this to our attention.

    Thanks,
    Erin