Part Number: DAC81404
Hi TI support team,
I am currently dealing with an issue with DAC81404. I coud not establish the communication between my ARM board and DAC81404. Can you please help me confirm the correct SPI mode for this DAC? diagram (Figure 7-1) shows SCLK idle low with data captured on the falling edge, is this CPOL=0, CPHA=1 (Mode 1)? What is the minimum required initialization sequence before the first register read is valid? Specifically: is a soft reset required, and must DEV-PWDWN be cleared before SDO will drive any data back?
Thank you for any feedback

