Part Number: ADS8354
In addition, For Both Channel A and B
Reference = 2.52V, input = 1.29V
Both circuits are identical (please refer to ADS8354 schematics
ADC read frequency is 500ms.
CFR REg is set to = 0x8600 - Single SDO mode 32 clocks, FSR = 2xVref
REFDAC_A and B - Default conditions.
with above settings, we see
channel A - ADC count is more stable (refer to the table below)
Channel B - ADC count is difference is high (refer to the table below )
| annel B | Decimal | Difference | Channel A | Decimal | Difference | |
| DFE2 | 57314 | E024 | 57380 | |||
| E012 | 57362 | 48 | E026 | 57382 | 2 | |
| E012 | 57362 | 0 | E024 | 57380 | -2 | |
| E012 | 57362 | 0 | E029 | 57385 | 5 | |
| DFE2 | 57314 | -48 | E020 | 57376 | -9 | |
| DFF2 | 57330 | 16 | E01E | 57374 | -2 | |
| E012 | 57362 | 32 | E028 | 57384 | 10 | |
| E012 | 57362 | 0 | E01F | 57375 | -9 | |
| DFE2 | 57314 | -48 | E023 | 57379 | 4 | |
| E012 | 57362 | 48 | E023 | 57379 | 0 | |
| DFDA | 57306 | -56 | E028 | 57384 | 5 | |
| E012 | 57362 | 56 | E027 | 57383 | -1 | |
| DFD2 | 57298 | -64 | E02F | 57391 | 8 | |
| DFD2 | 57298 | 0 | E026 | 57382 | -9 | |
| E012 | 57362 | 64 | E021 | 57377 | -5 | |
| E012 | 57362 | 0 | E026 | 57382 | 5 |
wanted to know why the change in ADC values and whre could be the problem?