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DAC39RFS10EF: PLL to use for DAC39RFS10EF subclass0 system

Part Number: DAC39RFS10EF
Other Parts Discussed in Thread: DAC39RFS10, , LMX1204, LMK04208, LMK04828, LMX2594, LMX2820

Hi All

We're studying reference designs for the DAC39RFS10/EF. In our targeted application we only have a single converter system: Kintex 7 FPGA --> DAC39RFS10EF. To my understanding a subclass0 JESD204 architecture would be sufficient.

We're intending to run max 6.6Gbps (FPGA GTX limit) on 8 lanes to achieve a sampling rate of about between 2 and 4 GSPS (while 3.878 GSPS seems to be the max out of the EF DAC at 64b/66b).

In the reference designs I see there are powerful and expensive PLLs used such as the LMX1204 and LMK04828. To me they seem to be an overkill for our application. Can we use also the LMK04208? It does not have dedicated SYSREF outputs and has a slightly worse jitter. 

Other question: shall we best clock the DAC with the 1:1 sampling rate, so at 3.2'ish GHz or is it reasonable to use the DAC's internal PLL? Maybe the latter has worse performance? Actually I see that both LMK04828 nor LMK04208 go beyond 3.07 GHz. Would that cap our sampling rate to 3 GSPS?

  • Hi All, any update on this?

    thanks, Adrian

  • The DAC39RFS10EF does not have an internal PLL, so an external clock is required. LMK would limit the DAC's output frequency and also please note the phase noise would be degraded heavily. We recommend something like an LMX1204 due to its very low additive phase noise, which does not degrade the performance of the DAC39RFS10EF

  • Hi Bill

    Thanks for the reply. That was a misconception of mine then that the DAC39 has an internal PLL for that.

    So, using any of the LMX family PLLs with JESD support would be suitable for our application? As said, we have a single DAC on the FPGA, subclass0 would be enough. Sampling rate of 3-4 GHz is ok as we anyway are limited by using the EF export friendly version of the DAC39. What about the LMX2594 or LMX2820 then? However, I see JESD support seems to refer to SYSREF generation, so that might not even be needed?