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DAC11001B: Glitch, Temperature calibration, ROFS|RFB matching

Part Number: DAC11001B

Hallo, 

I have a couple of questions thas have not been cleared up for me by the datasheet: 

  • How long does the temp calibration process take typ. and worst case?
  • How good is the matching of the ROFS|RFB resistors and woutd it make sense to include this value in the electrical characteristics section of the datasheet (or did I just miss it)?
  • Looking at Fig.  6-31 and 6-32 the glitch occures roughly 1.4us after the falling edge of LDAC. I wonder why this is so late. What setting of UP_RATE was used for these figures and I would be very interested to see what UP_RATE=01 look like? 

Sincerely 

Jens

 

  • Hi Jens,

    Please check my response below - 

    How long does the temp calibration process take typ. and worst case?

    [Sanjay] >>  It's ~2.5ms typical. 

    How good is the matching of the ROFS|RFB resistors and woutd it make sense to include this value in the electrical characteristics section of the datasheet (or did I just miss it)?

    [Sanjay] >>  Here is typical device data (there is no spec for this though)
    DUT#1 - 
    R(ROFS-RCM) = 5.2128k ohm & R(RCM-CFB) = 5.2034k ohm

    DUT#2 - 
    R(ROFS-RCM) = 5.1208k ohm & R(RCM-CFB) = 5.1110k ohm

    DUT#3 - 
    R(ROFS-RCM) = 5.1982k ohm & R(RCM-CFB) = 5.1901k ohm


    The matching error is in range of 0.156% to 0.191%


    Looking at Fig.  6-31 and 6-32 the glitch occures roughly 1.4us after the falling edge of LDAC. I wonder why this is so late. What setting of UP_RATE was used for these figures and I would be very interested to see what UP_RATE=01 look like?

    [Sanjay] >> Let me check and will get back to you by early next week.

    Thanks,
    Sanjay

  • Hi Jens,

    Regarding the Fig.  6-31 and 6-32 on glitch - 
    1. 1.4us times is combination of digital operation and TNH circuit (track and hold). 
    2. In this case the UR_RATE is = 0x10 (lowest update rate.
    3. Setting the UR_RATE = 0x01 would not have any wors impact on the glitch energy (it would reduce the time between the two large flitch Fig. 6-31). But it will degrade the dynamic performance i.e. - THD of this device.  



    Di let us know for any further help.

    Thanks,
    Sanjay