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ADC124S021: Maximum delay from /CS falling edge to first SCLK and intermittent abnormal output codes

Ryu Yamashita
Genius 4845 points

Part Number: ADC124S021

Hi team,

Since I have not received a reply, I am reposting this.
 
Background: We are using ADC124S021CIMMX to measure a thermocouple-related signal on IN4. The analog input voltage appears stable, but the ADC output code intermittently changes abnormally. In our current timing, /CS is driven low and the SCLK burst starts approximately 4 ms later. The burst contains 16 SCLK cycles.
Questions:
  1. Is there any maximum allowed delay from /CS falling edge to the first SCLK edge when /CS is held low?
  2. If /CS is held low for several milliseconds before the 16-clock burst, can SCLK glitches or missed edges cause the internal serial state to shift without automatic timeout recovery?
  3. Does TI recommend toggling /CS high after every 16-clock frame to re-synchronize the interface for this device?

Best Regards,
Ryu.

  • +1
    TI__Mastermind 20790 points

    Hello Yamashita-san,

    My apologies for the delay in response, as I was on leave.

    Can you clarify what is the measured input voltage, what is the measured voltage of VA, and what digital output are you receiving?

    1. There should not be a limit on the time between the fall of ~CS and when SCLK becomes active. The input signal remains in acquisition for the first 3 SCLK cycles, which does limit the minimum SCLK frequency, as voltage can leak from the sampling capacitor between sampling and conversion phases if too much time elapses and yield an error.

    2. We have not observed this behavior. However, it is possible glitches on SCLK can cause desynchronization between the device and controller. 

    3. If there is an extended amount of time between samples, it is a good idea to bring ~CS high between samples periodically to ensure synchronization.

    Are you able to give more information of the timing, such as the time between samples, SCLK frequency, and whether there are any other factors that seem to cause the issue to occur more or less frequently? Can you also share a schematic of the application?

    If more time is allowed between samples, or less time between the fall of ~CS and when SCLK is active, is there any difference in how frequently an issue occurs?

    Regards,
    Joel