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ADC08D1520 Dual Edge Sampling (DES)

Richard Elmquist
Mastermind 45250 points

Other Parts Discussed in Thread: ADC08D1520

I have a customer who is having problems using the ADC08D1520 in DES mode. He is seeing the following issue:

I'm having difficulty configuring the ADC08D1520 for Dual Edge Sampling (DES). I am in DES 1:4 Demux mode by programming the SPI with test data using bit stream "0000 0000 0001 1001 1010 0010 1111 1111" = 0x19A2FF to address the extended configuration register. I also configure the configuration register with bit stream "0000 0000 0001 0001 1011 1110 1111 1111" = 0x11BEFF to enable DDR Demux. I obtain the correct test data out. 01 02 03 04 fe fd fc gb... etc. as illustrated in page 36, Table 6: "Test Pattern by Output Port in 1:2 Demultiplex Mode".

When I configure the SPI out of test mode, 0000 0000 0001 1001 0010 0010 1111 1111 = 0x1922FF by setting address 9h, bit 15 to '0', I obtain what looks to be my desired triangle wave. When looking at the data in hexdump, I see uneven sampling. Here is the data that I receive near 7f/80, the most linear part of the triangle wave:

7f 7b 7b 77 76 72 72 6e 6d 6a 69 65 64 61 60 5c ...

If you count the spacings in between each consecutive sampling, you will get 4 (7f to 7b), 0 (7b to 7b), 4 (7b to 77), 1, 4, 0... etc.

This could be explained that both converters are sampling at the rising and falling edges of DCLK+ and DCLK- . It seems both converters are sampling at the same time, and I do not want that. So I would like to offset one clock or one channel so that I have an even spacing between channels. In this example, I want data to look like

7f 7d 7b 79 77 75 73 71 6f 6d 6b ...

If you could point out in the manual or instruct me how to set up the configuration register and extended configuration register to achieve these even spacings in DES mode, that would be most helpful for me.

Is he interleaving the data improperly or is there a problem with his set-up?

Thanks for your help with this issue.

Richard Elmquist

  • 0
    TI__Mastermind 44680 points

    Hi Richard

    Reviewing the output test pattern data and register settings, it appears the configuration of the sampling mode and the processing of data are correct.

    The triangle wave data also confirms that the device definitely is in DES mode. (if not, one channel of data would be close to mid scale, or at least vastly different than the other).

    The key issue appears that there is an offset between the I/Id and Q/Qd channels. It may be possible that the device has not been re-calibrated once the settings have been updated to the desired configuration. Failure to properly calibrate can lead to offset and full scale range errors between the interleaved channels, among other things. See section 2.4.2 of the datasheet for full details on device calibration.

    I would recommend the customer works with the current setup, but then performs an on-command calibration as described in Section 2.4.2.2 of the datasheet. Hopefully this will resolve the problems. If the problems persist, please let me know.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    TI__Mastermind 45250 points

    Jim,

    Your answer solved the issue for the customer, but he has an additional question regarding DES mode:

    In order properly to set Offset and FSR while in DES mode, does one write the same values to both I-Channel and Q-Channel? In DES mode, I wrote to I-Channel only and that caused my data to flare. Let me know if I'm correct on this.

    Is the customer correct in that the same values need  to be written to both channels or is he seeing another issue with his setup?

    Thanks for your help!

    Richard Elmquist

  • 0 in reply to Richard Elmquist
    TI__Mastermind 44680 points

    Hi Richard

    The customer is correct. In DES mode, the separate I channel and Q channel Offset and FSR registers must both be adjusted as desired. Selecting DES mode changes the input muxing and internal ADC clocking only.

    Best regards,

    Jim B