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Original question:

LSF0102-Q1: LSF0102QDCURQ1 hardware design support

LSF0102-Q1: Sleep mode current consumption

Prafulla Salunke
Prodigy 70 points

Part Number: LSF0102-Q1
Other Parts Discussed in Thread: TXU0202, TXS0102

Hi There, 

For below mentioned configuration of LSF0102-Q1, IC is consuming ~25uA current during sleep mode. During sleep mode:

  1. 3.3V_BLE = 0V, 5V_MCU  = 5V will be available. 
  2. B1 & B2 are pulled up with 1k. 

I need to put IOs in tristate mode during sleep mode. What can be the best possible way ?

  1. Can I connect OE w.r.t Vref_A=3.3V_BLE. Since It is not available during sleep so OE will not trigger internal FETs ?
  2. Do I need to drive OE from MCU I/O tolerant to 5V ? Is it allowed ? In that case whether OE still needs to be shorted with Vref_B ? 
  3. image.png
  • 0
    TI__Guru 58631 points

    Hello,

    We are still looking into this and will follow up shortly.

    Regards,

    Jack

  • 0 in reply to Jack Guan
    TI__Intellectual 865 points

    Hi 

    The measured current of approximately 25 µA during sleep mode is expected. When VREF_A is at 0 V while the 5-V supply remains available, current flows from the VREF_B/EN bias network through the internal bias FET toward VREF_A. Based on the 200-kΩ bias resistor, the estimated current is approximately:

    I_BIAS ≈ (5 V − 0 V − VTH) / 200 kΩ ≈ 21 to 22 µA.

     

    To place the A1/B1 and A2/B2 channels into high-impedance mode, EN must be pulled LOW. However, EN should not normally be driven directly by a push-pull MCU output, because EN and VREF_B form part of the device’s internal bias circuit.

    The recommended implementation is:

    • Keep EN directly connected to VREF_B.
    • Keep the required 200-kΩ resistor from the 5-V supply to the EN/VREF_B node.
    • Use an open-drain MCU output or an external open-drain NMOS to pull the EN/VREF_B node LOW during sleep.
    • Release the open-drain control when normal operation is required.

     

    Therefore, connecting EN directly to the switched 3.3V_BLE rail is not recommended for normal operation, because EN must be connected to VREF_B to correctly establish the internal FET bias. When EN is LOW, all I/O channels are placed in the high-impedance state.

    Brian

  • 0 in reply to Brian Lin (TXP)
    Prodigy 70 points

    Hi Brian, 

    Thanks for your detailed explanation. I agree with this approach to drive OE through open drain MCU pin or external FET. This will surely help to IOs in tristate mode. But still 22uA will flow through external switch. 

    Means, still in sleep mode (target max value of PCB is 50uA), 22uA is through level shifter will be there. 

    Is there any other solution where this 22uA can also be reduced completely ? Can other solutions like TXS0102 or TXU0202 can be used ? 

    Regards, 

    Prafulla S. 

  • 0 in reply to Prafulla Salunke
    TI__Intellectual 865 points

    Hi Prafulla ,

    I would suggest TXU0202 that can minimize the power consumption (2.5uA max at room temp). Thanks.

    Brian