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DAC63001: Comparator latch behavior on OUT0 pin

Danilo A.
Mastermind 34425 points

Part Number: DAC63001
Other Parts Discussed in Thread: DAC63204-Q1

Hi Team,

Posting on behalf of our customer.

I will share this post with our customer so he can reply when needed.

We are using the DAC63001 as a programmable comparator/latch in an electronic circuit breaker application. We would like to confirm the correct register configuration and expected behavior of the comparator latch on the physical OUT0 pin.

Channel used: DAC0 / FB0 / OUT0
Supply/reference: 3.3 V
Comparator input: FB0
Required behavior: OUT0 should latch after FB0 crosses the programmed threshold, and should reset only after writing RST-CMP-FLAG-0.

Our intended behavior is:

Safe/no trip: OUT0 high
Trip: OUT0 low
OUT0 must remain latched after threshold crossing
Latch reset by writing COMMON-DAC-TRIG.RST-CMP-FLAG-0 = 1

Current tested configuration:

DAC0-MARGIN-HIGH      address 0x13 = 0x0120   // approx. 15 mV threshold
DAC0-MARGIN-LOW       address 0x14 = 0x0000   // zero-code
DAC0-CMP-MODE-CONFIG  address 0x17 = 0x0400   // CMP-X-MODE = 01, hysteresis mode
DAC0-VOUT-CMP-CONFIG  address 0x15 = 0x000D   // CMP-X-EN=1, CMP-X-OUT-EN=1,
                                               // CMP-X-HIZ-IN-DIS=1, CMP-X-INV-EN=0
COMMON-CONFIG         address 0x1F = bit15 set // WIN-LATCH-EN = 1
COMMON-DAC-TRIG       address 0x21 = 0x000E   // RST-CMP-FLAG-0,
                                               // TRIG-MAR-LO-0,
                                               // TRIG-MAR-HI-0

We also tested COMMON-CONFIG.WIN-LATCH-EN = 0.

Observed behavior:

With CMP-X-MODE = 01 and MARGIN-LOW = zero-code, the OUT0 pin behaves as a comparator/hysteresis output, but does not latch as expected.
When FB0 crosses the threshold, OUT0 changes state.
When FB0 returns below the threshold, OUT0 also returns, instead of remaining latched.
Writing RST-CMP-FLAG-0 does not appear to be the only thing controlling the output state.
In window comparator mode, WIN-LATCH-EN appears to latch internal status, but the physical OUT0 pin does not behave like a latched output. This seems consistent with the datasheet statement that the static behavior of WIN-CMP-X is not reflected at the output pins.

Datasheet reference:

The datasheet states:

“When the DAC-X-MARGIN-HIGH is set to full-code or the DAC-X-MARGIN-LOW is set to zero-code, the comparator works as a latching comparator; that is, the output is latched after the threshold is crossed.”

We are trying to understand precisely what “output” means in this sentence for hysteresis comparator mode: does it refer to the physical OUT0 pin, or to an internal comparator status bit?

Questions:

For CMP-X-MODE = 01 hysteresis comparator mode, should the physical OUT0 pin latch when MARGIN-LOW = 0x0000?
Is COMMON-CONFIG.WIN-LATCH-EN relevant only to window comparator mode, or should it also be enabled for hysteresis latch mode?
Is TRIG-MAR-HI-0 / TRIG-MAR-LO-0 required after writing DAC0-MARGIN-HIGH and DAC0-MARGIN-LOW for comparator thresholds to take effect?
What is the recommended register sequence to configure DAC0 as an active-low latching comparator on OUT0?
For active-low latch behavior similar to datasheet Figure 7-6, should the configuration be:
MARGIN-LOW = 0x0000
MARGIN-HIGH = threshold
CMP-X-MODE = 01
CMP-X-INV-EN = 0
CMP-X-OUT-EN = 1
Is there any additional register, status bit, GPIO mapping, or NVM/default behavior that must be configured to make OUT0 latch physically?

Any example register sequence for DAC63001 configured as a physical OUT0 latching comparator would be very helpful.

Regards,

Danilo

  • 0
    TI__Mastermind 24565 points

    Hi Danilo,

    I believe this is related to the offset error of the margin low setting. The 0x0000 code might not be exactly 0V. I'm currently looking into more details about this to see if there's a quick fix or if it's a hardware limitation.

    Regards,

    James

  • 0 in reply to James Steenbock
    TI__Mastermind 24565 points

    Hi Danilo,

    I still haven't received a response about the exact comparator behavior regarding the 0x0000 margin low setting, but regarding some of your other questions:

    Danilo A. said:
    DAC0-MARGIN-HIGH      address 0x13 = 0x0120   // approx. 15 mV threshold
    DAC0-MARGIN-LOW       address 0x14 = 0x0000   // zero-code
    DAC0-CMP-MODE-CONFIG  address 0x17 = 0x0400   // CMP-X-MODE = 01, hysteresis mode
    DAC0-VOUT-CMP-CONFIG  address 0x15 = 0x000D   // CMP-X-EN=1, CMP-X-OUT-EN=1,
                                                   // CMP-X-HIZ-IN-DIS=1, CMP-X-INV-EN=0
    COMMON-CONFIG         address 0x1F = bit15 set // WIN-LATCH-EN = 1
    COMMON-DAC-TRIG       address 0x21 = 0x000E   // RST-CMP-FLAG-0,
                                                   // TRIG-MAR-LO-0,
                                                   // TRIG-MAR-HI-0

    This register sequence should be sufficient to enable the latching comparator mode. However, you do not need the WIN-LATCH-EN bit for the hysteresis mode. That bit is only used for the window comparator mode.

    In the window comparator mode, you do not need to trigger the margin high or low. The settings are used for the thresholds without any trigger needed. The triggers are only for slewing the output voltage to the margin levels in voltage output mode.

    I have another thread about this where the hysteresis latching seems to work as expected, EXCEPT when the comparator input voltage returns to 0V. At the moment you have a margin high threshold of 15mV, so it's possible that the zero code offset error is causing the latch to release quite soon after your input voltage drops below 15mV. According to the datasheet, the zero-code error has a max spec of 15mV, so your real hysteresis might be thinner than the ideal expectation.

    You could verify the latch functionality by raising the margin high threshold to a greater code value and see if you achieve the expected behavior. You should see the OUT0 voltage remain low even after the input falls back below the margin high threshold. After that, I'm expecting the latch to be released if you change the input to the comparator to 0V because of the zero-code offset error. This is what I'm asking about internally to see if there's some way to overcome the offset, or if this is unavoidable device behavior.

    Regards,

    James

  • 0 in reply to James Steenbock
    TI__Mastermind 24565 points

    Hi Dani,

    Just a quick follow up. I confirmed that the latching behavior is affected by comparator input offset. Even when margin low is set to zero-code, an input voltage that measures below the offset error can cause the latch to release. I had to check if there were any other conditions for the latch, but the internal digital logic isn't doing anything special.

    Regards,

    James

  • 0 in reply to James Steenbock
    Prodigy 30 points

    Hi James,

    Thank you for the clarification. We have already tested the comparator with significantly higher MARGIN-HIGH thresholds, well above the specified 15 mV maximum zero-code error.

    The observed behavior remains the same:

    When FB0 rises above MARGIN-HIGH, OUT0 goes low.
    When FB0 falls back below MARGIN-HIGH, but remains above zero, OUT0 remains latched low.
    When FB0 returns to approximately 0 V, OUT0 returns high without writing RST-CMP-FLAG-0.

    Therefore, the issue does not appear to be caused only by the 15 mV threshold being comparable to the maximum zero-code error.

    The zero-code error could explain some variation in the exact input voltage at which the output releases, but it does not explain why reaching the lower threshold releases the latch without a reset command.

    Could you please confirm internally whether crossing the effective MARGIN-LOW threshold automatically clears the hysteresis latch?

    More specifically, with:

    MARGIN-LOW = 0x0000
    MARGIN-HIGH set well above the zero-code error
    CMP-X-MODE = 01

    should the physical OUT0 pin remain low when FB0 returns to 0 V, until RST-CMP-FLAG-0 is written?

    This distinction is important for our electronic circuit-breaker application because, after a trip, the measured current naturally returns to zero. If returning to zero automatically releases the comparator output, the device cannot provide a persistent hardware trip latch.

    Also toggling the RESET_CMP_FLAG_1 bit causes the comparator to alternate between a triggered and non-triggered output, like described by Daniel Studer87 for the DAC63204-Q1,

    Regards, Celso

  • 0 in reply to Celso Colaco
    TI__Mastermind 24565 points

    Hi Celso,

    To clarify, the latch is designed to release when the signal crosses below MARGIN LOW. This is the normal hysteresis behavior. Setting the margin low to the zero-code is theoretically supposed to keep input from crossing the low threshold and, by extension, create a latched output that only releases upon reset.

    However, If the zero-code has some offset error that results in the REAL margin low sitting at around 15mV, then any input to the comparator that falls below 15mV will cause the latch to release.

    Also, I verified the toggle behavior when using the RESET-CMP-FLAG-0 bit. This doesn't seem like the intended function of this bit, so I have to take that feedback to the team. For now, you should only send the reset when the comparator is tripped.

    Regards,

    James

  • 0 in reply to James Steenbock
    Prodigy 30 points

    Hi James,

    As a possible workaround, would it be valid to introduce a small positive bias voltage on FB0 so that our “zero current” condition never brings the comparator input down to the DAC63001 zero-code region?

    For example:

    0A current would be FB0 = 50 mV
    A Trip threshold signal = 200 mV
    So the effective trip level will be at FB0 = 250 mV
    MARGIN-LOW = 0x0000
    MARGIN-HIGH = code corresponding to 250 mV

    The idea would be that, after a trip, when the current falls back to zero, FB0 would return to approximately 50 mV instead of 0 V. This should keep the input above the effective zero-code / lower-threshold region and hopefully prevent the latch from releasing unintentionally.

    Then the latch would only be cleared intentionally by writing `RST-CMP-FLAG-0`.

    Would this be a valid and reliable workaround for the zero-code offset behavior?

    Regards,

    Celso

  • 0 in reply to Celso Colaco
    TI__Mastermind 24565 points

    Hi Celso,

    Yes, this idea would work.

    If you can keep your lowest input to the FB pin at or above 50mV, then the latch would hold until the reset bit is toggled. 

    Regards,

    James