ADS4142: Driving ADC

Part Number: ADS4142
Other Parts Discussed in Thread: SN65LVDS9638, LMK6D,

Hello TI Team,

I am designing a system using a high-speed pipeline ADC with the following conditions:

• ADC analog supply: 1.8 V

• ADC digital output: LVDS

• ADC sampling clock: 30 MHz differential LVDS

• Input signal frequency: 7.5–10 MHz

• Sampling frequency: 30 MHz

• Differential amplifier (FDA) planned before the ADC

I would appreciate your guidance on the following questions.

1. ADC Input Without FDA

• What happens if I drive the ADC directly without using the FDA?

• Can I apply a single-ended signal from a function generator directly to the ADC by connecting the positive input to the signal and grounding the negative input?

• Will the ADC still operate correctly, and what performance degradation should I expect?

• If I want to evaluate the ADC separately from the FDA, what is the recommended test setup?

2. RC Input Filter

• If I do not use the  RC filter between the FDA and the ADC, what impact will it have on ADC performance?

• Is the RC filter mandatory, or can the ADC be evaluated without it during initial testing?

3. Measuring ADC Performance

• How can I measure SNR and ENOB in the laboratory?

• My input signal is a pulse/pseudo-digital waveform around 7.5–10 MHz rather than a pure sine wave. Can SNR and ENOB still be evaluated with this type of signal, or is a low-distortion sine-wave source required?

4. Differential Clock

For the ADC clock, I plan to use:

• 30 MHz low-jitter oscillator

• SN65LVDS9638 to convert the single-ended oscillator output to differential LVDS

Will this be an appropriate approach for obtaining a clean, low-jitter ADC sampling clock, or would TI recommend a simpler clock-generation solution?

5. Clock Termination

If the differential clock is supplied externally through an SMA connector, is differential termination required at the ADC clock input?

Similarly, if the clock is generated on the PCB using an oscillator and LVDS driver, is a termination resistor still required?

6. High-Speed PCB Test Points

What type of test points are recommended for high-speed analog and clock signals?

Would  dedicated probe pads be preferred for measuring or connector of header after jumper will be connected tell how much distance between them is required.

• Differential analog inputs

• Differential ADC clock

• High-speed LVDS signals

7. FPGA Interface

The ADC operates at 1.8 V, while my FPGA I/O is 3.3 V.

• Should the SPI control signals (CS, SCLK, SDIO) be level shifted from 3.3 V to 1.8 V?

• Is a unidirectional or bidirectional level shifter recommended?

• If a level shifter is not required, what is the recommended interface method?

Thank you for your guidance and recommendations.