Part Number: ADS1288
Hello,
We are working on a new design and looking at the ADS1288 for the ADC. It is especially attractive because of its high resolution and low power consumption. Our plan is to run with a single 5Volt supply connected to both AVDD1 and AVDD2, and a 1.8Volt supply for IOVDD.
The application is battery powered, and during times when the system is not acquiring data, we are aiming to power down as much of a the system as we can. While the ADC draws very little current in power down, there are other components on the 5Volt supply, so we need to power this off to reduce the drain on the battery.
Is it possible to power down AVDD1 and AVDD2 (the reference would also be powered down), but keep the 1.8Volts applied to IOVDD? In this mode the clock would also be stopped.
If this is possible, are there any implications for the power draw on the IOVDD pin?
We can certainly drive the PWDNn and RESETn signals to a logic '0', but I can see that it is possible for the CLK signal to be at a logic '1', as well as the CSn signal.
Thanks,
Andrew
