Part Number: ADS127L14
Hi I am doing some development on the ADS127L14 SDADC and I seem to be running in to an issue with the number of clock pulses on the dclk line, and would like to also clarify the maximum supported clock speeds.
Note as we wish to capture the high resolution ADC data synchronus to an external trigger so we run the ADC in START/STOP mode using the low latency SINC4 filter. We simply have to pay the price of the added latency which reduces our sample rate on each ADC reading.
1) I have configured the ADC numerous different configurations with regard to the fmod and fdclk and OSR and I always seem to be 4 clock pulses short of what I am expecting.
Based on `fdata = fmod / OSR = fclk / (2*OSR)` in the data-sheet and `fdclk >= fdata * TDM * DATA_PACKET_SIZE` (equation 22 in the datasheet) I calculate:
N_TOTAL_BITS = TDM DATA_PACKET_SIZE <= fdclk / fdata = fdclk 2 * OSR / fclk`, so I should expect at least 2 * OSR * fdclk / fclk bits clocked out of the dclk pin.
I have done this for fclk = 28Mhz, fmod = 14Mhz, fdclk = 28Mhz (DIV1 for both DCLK and CLK) with a OSR of 24. I expect `N_TOTAL_BITS = 24 * 28Mhz/14Mhz = 48bits` so I can fit 2*24bit samples into this timing. However as seen from the scope capture below I am only seeing 44 dclk pulses (pink)?
I have also done this where I have the fclk = fdclk = 28Mhz and a DIV2 on the main clock, and I am expecting 4*OSR or 96bits, but again I only see 91bits clocked out as shown:
I have also done the same thing at various different OSR like 32, 16, and 12 with different modulator frequencies and START timing etc, and there is always 4 bits missing. This forces me to run the ADC much much slower than I would like as I need to waste 12bits or more to fit the data into the output packet. Is there some setting on the ADC I have missed that could cause the 4 bits to go missing? Or have I miss understood the ADC design (hopefully not because that would mean there are always wasted bits, and the data port never packs nicely) ?
2) Lastly I want to confirm the clock frequency limitations
Ttable 5.6 of the datasheet seems to show that the tc(CLKIN) and tc(DCLK) both have a minimum period of 15ns (66.7Mhz). But fclk is listed at a maximum of 33.66Mhz. Does this mean I can drive the CLKIN and DCLK to say 64Mhz and run the fclk at CLKIN / 2 for 32Mhz allowing me to shift the data out much much faster ? Its not clear as all the examples etc seem to use 32.768Mhz as the maximum input clock, and I just want to confirm its ligit to run the CLKIN and DCLK at the full 64Mhz ?
Thank you for any help you can offer and if you need more details on the setup please let me know.