DAC161S997: DAC161S997 SPI rise/fall time

Fabian Hladik

Part Number: DAC161S997

Dear TI support team,

we plan to use the DAC161S997.

We need isolation for SPI.

Due to the significantly lower cost and the fact that we do not need a fast update rate, we would like to use optocouplers instead of logic isolator ICs.

This comes with the disadvantage of slow rise/fall times (hundreds of µs).

The DAC161S997 does not specify any minimum rise/fall time for the SPI interface.
Are very slow signals (e.g. 500 µs rise/fall time) acceptable?

Specific concerns:

What is the input structure of SCLK, SDI and CSB?
Could slow edges lead to increased current consumption due to the input stages?
Could slow edges lead to double clock pulses on SCLK?

A technical assessment of the acceptable rise/fall times and any potential limitations would be appreciated.

11 days ago

0 Lucas Burnette 10 days ago

TI__Expert 5860 points

Hi Fabian,

Let me look into this and I will get back to you shortly.

Thank you,
Lucas

0 Lucas Burnette 9 days ago in reply to Lucas Burnette

TI__Expert 5860 points

Hi Fabian,

I am waiting on a response from my team and will update you when I have more information.

Thank you,
Lucas

0 Lucas Burnette 8 days ago in reply to Lucas Burnette

TI__Expert 5860 points

Hi Fabian,

There will tend to be higher DC currents on the VIO supply and potentially more noise or glitches on the digital lines.

Slow rise/fall time digital signals are still acceptable, but may need to be tested to ensure your system has low enough noise that the digital thresholds of the SPI work as expected.

Here is an example of how the current is impacted by the voltage level (for a different DAC):

Thank you,
Lucas

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DAC161S997: DAC161S997 SPI rise/fall time