Part Number: ADS1220
I have isolated the following timing issue with the ADS1220.
The device is configured as follows:
- Gain: 4
- PGA: enabled
- Reference: REFP0–REFN0
- Digital filter: FIR 50/60 Hz rejection
- IDAC current: 1000 µA
- Operating mode: Normal
- Data rate: 20 SPS
- Conversion mode: Continuous
- Temperature sensor: disabled
- Burnout current sources: off
- Internal oscillator
The issue can be reproduced with the following sequence:
- Configure MUX and IDACMUX.
- Wait for a delay (T_d).
- Send the START/SYNC command.
- Wait for DRDY to go low.
- Read the conversion result using RDATA.
repeat form 1.
I am aware that changing the MUX configuration restarts the ongoing conversion. However, in my application I need to allow a few additional milliseconds for the analog circuitry to settle before starting the conversion that will actually be used. This is the reason for the delay (T_d) followed by the START/SYNC command.
In most cases, the behavior is as expected: DRDY goes low approximately 50 ms after the START/SYNC command.
However, when (T_d) is approximately 3.12 ms, 6.24 ms, 9.36 ms, and so on, DRDY instead goes low only about 3.1 ms after the START/SYNC command.
The issue appears periodically at approximately 3.12 ms intervals, and the timing window is quite narrow, roughly ±50 µs.
Interestingly, if I replace the START/SYNC command with another MUX configuration write, the issue disappears and DRDY behaves as expected.
Is this behavior related to the internal digital filter timing or synchronization of the START/SYNC command in continuous-conversion mode? Is this a known or documented behavior of the ADS1220?