ADC12SJ800: Request for ADC12SJ800 Reference Design

Please request a JESD204C IP at this link: https://www.ti.com/tool/TI-JESD204-IP

It would also be helpful to share the JMODE & sample rate requested for ADC12SJ800

Hi Clarke,


The sample rate is 800MSPS and JMODE 0 is used


Thanks and Regards

Deeksha N

Hi Clarke,

It is not JMODE 0. Our requirement is for the JESD204C IP to use 64b/66b encoding, with 2 lanes and an ADC sampling rate of 800 MSPS.

Could you please suggest the appropriate JMODE configuration for this requirement? We are currently confused between JMODE 6 and JMODE 14.

We are providing a 200 MHz clock to the ADC from the clock generator.

Please let us know which JMODE would be the appropriate configuration for our requirement.

For 12-bit, single-channel, 2 lanes you could use either JM6 or JM14. I recommend JM14 as its LMFS packing is more efficient for a single channel and will operate at 800 MHz with a lower SerDes line rate compared to JM6.

Are you intending to use the PLL w/ 200 MHz reference frequency to achieve 800 MHz sampling rate?

Yes Clarke, We are using the PLL w/ 200 MHz reference frequency to achieve 800 MHz sampling rate.
Now we have shifted to 4 lanes and JMODE 15 will be appropriate configuration for this. Can you please confirm
Whether we can obtain the ADC12SJ1600EVM FMC from TI on rental basis as there are no EVM for ADC12SJ800 card for development purpose?

Please order ADC12QJ1600 EVM, you can use the part in single channel mode to mimic ADC12SJ800 behavior