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ADS8354: ADS8354 connection to LMP91000

Gopal Savanur
Prodigy 30 points

Part Number: ADS8354
Other Parts Discussed in Thread: LMP91000, ADS8353

Below is my ADS8354 connections.

                                           

 

Current Design :

VREF = 2.5V,   AVDD = 5V,  DVDD = 3.3V, AINP_A – Connected to Vout pin of LMP91000

AINM_A – Connected to VREF

 

Question

  1. ADS8354 datasheet recommends to use TSH451 as input driver to connect LMP9100 Vout to ADC8354 AINP_A. Do we really need this?
  2. If I connect REFIO_A to external VREF, can we still use internal Reference of ADC8354? Should we have to disconnect external Reference when using Internal?
  • 0
    TI__Expert 7960 points

    Hello Gopal, 

    The ADS8354 is a fully differential ADC, meaning it has to comply to an input common mode voltage to ensure the fully differential performance 

    This means that the average between AINP + AINM should be VREF/2 ± 0.1V

    So to answer your questions, an FDA or a driving circuit capable of maintaining the common mode is needed.  

    Setting a fixed value on the AINM would limit the input range of AINP by ~±0.2V around AINM

    We do have another very similar device, pin-to-pin, and exactly the same in many ways, the ADS8353. This is the Single-ended/Pseudo differential variant of the ADS8354

    With the ADS8353, an opamp can be used to drive the AINP and the AINM can be set to GND, VREF/2, or VREF.

    For your second question, if the internal reference is being used, I would recommend the external reference be disconnected. Both REFIOs should also not be shorted together when using the internal reference either. Since they have 2 independent reference this could lead to overdriving them

    The schematic below is from the ADS8354EVM, it shows the connections between the REFIOs, the external reference, and the common mode drivers for the differential use case. In the schematic below, if the external reference was used then JP7 and JP9 can be shorted (external reference enabled within device), and if the internal reference is being used then JP7&9 should be open. 

    In both cases decoupling the REFIO pins is still recommended. 

    In the schematic shared in your post I would recommend maintaining the external reference. Could you please share what is the source of the external reference? 

    Best regards, 

    Yolanda