Part Number: ADC3649
Other Parts Discussed in Thread: LMK04610
Hello,
I am using the ADC3649 and trying to monitor the SYSREF input using the SYSREF_DET bit (Register 0x140, Bit 6). However, the register always reads 0x00 regardless of the input.
[My System Setup]
- Sampling Clock: 500 MHz
- SYSREF Input: Single-ended 1.8V CMOS via GPIO0 pin.
- SYSREF Signal: 2 consecutive pulses of 10ns width (spanning 5 clock cycles each)
[Background / Goal] My system consists of two ADC3649s, both receiving their sampling clocks and SYSREF from a single LMK04610. I understand that SYSREF is not strictly required for the ADC itself when operating in DDC bypass mode. However, I want to use SYSREF to synchronously reset the internal Ramp test patterns across both ADCs. This perfectly synchronized Ramp pattern is critical for our downstream FPGA to resolve the phase ambiguity and uncontrollable logic skew caused by the SERDES and clock-divider (BUFR/ISERDESE2) asynchronous reset releases. Therefore, I need to reliably capture and align SYSREF using Reg 0x140.
[ADC Configuration]
- Reg 0x146 = 0x00 (GPIO0 configured as SYSREF)
- Reg 0x160 = 0x00 (SYSREF Mode: Pass all SYSREF pulses)
- Reg 0x169 = 0x00 (DDC Bypass)
- Reg 0x102 = 0x40 -> 0x00 (Manual clear of SYSREF_DET prior to issuing the pulse)
[The Issue] After clearing Reg 0x102 and issuing the 10ns x2 SYSREF pulses, reading Reg 0x140 always returns 0x00. The SYSREF_DET bit is never set, and the X1-X5 flags are also completely unresponsive.
[Troubleshooting Performed (Hardware/Electrical causes ruled out)]
- Logic Analyzer/Oscilloscope: Confirmed that the 10ns pulses are perfectly reaching the GPIO0 pin.
- Pulse Width / Phase Independence: I tested with both 10ns (5 clock cycles) and 100ns (50 clock cycles) SYSREF pulse widths. Since these pulses span many sampling clock cycles, they should absolutely be level-sampled as HIGH regardless of the phase alignment or the X1-X5 window. However, both tests resulted in 0x00.
- Voltage Level (VIH) Verified via Timestamp: To prove the 1.8V CMOS input buffer is seeing the signal, I changed the SYSREF signal to a 5MHz continuous clock and enabled the SYSREF Timestamp function. The LSB of the ADC output data perfectly toggled at 5MHz
- Phase Sweep Performed: To eliminate the possibility of the SYSREF edge constantly hitting a metastable zone or falling outside a narrow detection window, I swept the SYSREF delay across a full sampling clock period (>2000ps) in ~60ps steps using the LMK04610's delay elements. Reg 0x140 remained 0x00 across all phase combinations.
This proves that the physical SYSREF signal perfectly meets the electrical thresholds and is reaching the internal digital core. However, only the SYSREF monitor register (0x140) seems to be dead/bypassed.
[My Questions]
- Are there any undocumented conditions, register settings, or specific operational modes (e.g., Test Pattern mode, DDC bypass) that internally disable the SYSREF monitor circuit (Reg 0x140)?
- Is there a specific initialization sequence required to enable the SYSREF_DET logic?
- Is there any known errata regarding Reg 0x140 for the ADC364x family?
Thank you for your support.