ADS1256: MUXCYCLING PROBLEM

hello Bryan which format do you prefer? 

...

WREG: 23h RDATA CH: 0000 0001

WREG: 45h RDATA CH: 0010 0011

WREG: 01h RDATA CH: 0100 0101

sorry it far away from been resolved 

Hi Jose de Jesus Colin Robles,

Do you have a schematic you can share?

Do you have logic analyzer captures that also show the data being captured in hex? See the image below for an example, I am not going to be able to do anything with the captures you sent unless I can actually understand what is being sent to and received by the ADC

How do you know the data is "mixing"? Are you applying 3 distinct input signals to your channels and the output data is a combination of the hex representation of each adjacent channel? 

What signals are you applying to the inputs?

Are you able to read one channel successfully without multiplexing? In other words, if you don't multiplex and just continuously measure a single channel is the data correct? If so, can you do this on all 3x channels and make sure the ADC can read each channel correctly individually?

-Bryan

As you can see, in this plot red line (CH2) has a sample from green line (CH3). This problem affects all channels.

when I read one channel, the data adquisition does not present this problem. Sigal is an square waveform of low frequency (10Hz). For schematic diagram, do you like the conections ADC-FPGA-CP? 

Hi Jose de Jesus Colin Robles,

In your logic analyzer captures, is the DOUT signal actually connected to the ADC DIN pin, while the DIN signal is actually connected to the ADC DOUT pin? 

Can you try toggling CS between commands - at least between SYNC and WAKEUP as well as WAKEUP and RDATA? Holding CS low means that the ADC will respond to anything on the SCLK pin, even transient noise. A single transient pulse on SCLK could desynchronize the entire communication sequence as a result. This communication scheme (3-wire SPI) is possible, but we do not recommend it.

-Bryan

Hello Bryan I really apreciate your help,

For pin asigment I have this: 

1) Din, ADS1256  --> Dout, FPGA. 

2) Dout, ADS1256 --> Din, FPGA. 

I tried to do your recommendation by setting CS high between commands and waiting period but with out success (ADS1256 is not responding). However I set CS high in serial send-receive periods (please see LOGIC ANALYZER) and I improve the signal Dout where there shouldn't be transitions. 

Expanding the Buffer of the logic analyzer I was able to identify undesired transitions from  ADS1256-Dout, pin despite CS is high and there is no command or SCLK signal, how is this possible?.

What do you recomend doing to improve SPI communication? This is the ADC used: 

. I hope you can help Here i put the analyzer captures: 

Hi Jose de Jesus Colin Robles,

I cannot tell why, but it looks like you have noisy communication

You can see that you've had these DOUT spikes in your previous scope shots as well, see the image below. Have you looked at the communication on a scope instead of a logic analyzer? That "blip" that looks like a digital transition might just be analog noise that rises above your analyzer logic threshold. In other words, you are getting noise spikes that the logic analyzer falsely shows as a digital transition.

As least in the case of the last image you sent, you can see these spikes occur right around the time that DRDY transitions high. Perhaps that signal is coupling onto the DOUT line and causing a disturbance? My best guess is that your signaling between your board and your FPGA are not very clean and that is causing issues with the communication

-Bryan

Hello Bryan thanks for your help, undesired transitions in Dout were removed but this wasn't the problem. 

ADS1256 requires more current than the FPGA can delivers . The solution was the use of decoupling capacitors in the 5V source voltage. Voltage drops make undesired resets in the FPGA.

Any way, thanks alot for your help.

Best regards

here is the proof thanks for your help, CH2 was the problem when the FPGA voltage dropped  

best regards Jesus C.