Part Number: DAC3161
Hello,
We are working on bringup of a new board which uses a DAC3161 driven by an FPGA. We are running into an issue where the iotest will not pass on any non-static values. If the pattern is set to either all 0s or all 1s and the FPGA produces the same, register 0x04 reports all lanes as passing. We have tested both with the standard patterns as well as a simple 1111_0000 sequence on each lane at a reduced 46MHz dataclk, but both tests show failures for all data lanes.
No other alarms are triggered except alarm_from_ iotesta. We have verified that the waveforms look correct on the scope, and there is plenty of timing margin at this speed.
Our config is as follows:
config0 - 0x02ED
config1 - 0xF007
config7 - 0x5F2F
and the rest are left at defaults.
Are there any other things we may be overlooking? Thanks all.
