Part Number: ADC32RF54
Other Parts Discussed in Thread: LMK04832, ADC12DJ3200, LMX2581, ADC32RF55EVM
Dear Technical Support Team,
As part of our review of the clocking scheme using ADC32RF54,
we have summarized our understanding regarding the phase synchronization method between SYSREF and the sampling clock.
Could you please review it and confirm whether there are any misunderstandings in our interpretation?
[Background]
Initially, we considered a configuration in which both the sampling clock and SYSREF would be generated by the LMK04832 alone.
However, we found that within the output frequency range of the LMK04832's internal VCO,
it is not possible to directly generate a sampling clock around,
for example, 2000 MHz, and therefore the desired sampling rates cannot be covered.
For this reason, similar to the ADC12DJ3200 design that we previously adopted,
we are considering a configuration in which SYSREF is generated by the LMK04832,
while the sampling clock is generated separately by a wideband synthesizer (such as the LMX2581).
After reviewing the ADC32RF55EVM schematic, we found that the external clock is connected directly to the ADC, and the LMK04832 is used exclusively for SYSREF (and FPGA-related clocks). We understand that this is a similar approach to the direction we are considering.
[Our Understanding]
Based on our review of the ADC32RF54/55 datasheet, there does not appear to be an internal automatic search function like the one provided in the ADC12DJ3200.
Our understanding is that the only implemented feature is a diagnostic monitor (register 0x22F) that reports the SYSREF window status.
Therefore, we believe that the only way to align the phase is to manually adjust the SYSREF output delay of the LMK04832 while repeatedly reading register 0x22F.
We do have one concern regarding this manual calibration method.
Register 0x22F only indicates whether SYSREF is inside or outside the invalid window, but it does not provide any information about the available timing margin.
As a result, if a value very close to the window boundary is selected, there is a risk that temperature changes or power supply variations could cause SYSREF to re-enter the invalid window.
We understand that the ADC12DJ3200 selects the center of the valid window for the purpose of securing sufficient margin. Likewise, for ADC32RF54/55, we believe that the delay value should be swept to identify both boundaries of the region where all bits in register 0x22F become zero, and then the midpoint of that range should be selected.
Could you please confirm whether this understanding is correct?
[Questions]
Q1
Is our understanding correct that ADC32RF54/55 does not have an internal automatic calibration mechanism,
and that manual searching using LMK04832 SYSREF delay adjustment combined with monitoring register 0x22F is required?
Q2
In the ADC32RF55EVM and TI software, is a similar manual calibration flow implemented (LMK04832 delay sweep + register 0x22F readback)?
Q3
Is it recommended for ADC32RF54/55 to select the center of the range in which all bits of register 0x22F become zero?
Q4
After the optimal delay value has been determined manually, is recalibration required whenever there are temperature changes or after a power cycle, or can the same fixed value continue to be used?
Q5
For a configuration in which SYSREF and the sampling clock are supplied by different devices, such as LMK04832 and LMX2581,
are there any recommendations or best practices that you could share?
Best Regards,
td
