ADS5407: syncing 5x ADS5407

Part Number: ADS5407

Hi team

We're phase-syncing 5x ADS5407 (10 channels) using a common SYNC pulse to all devices, per the recommended init sequence. On ~1 of 15 power cycles, a subset of channels ends up phase-shifted from the rest by exactly one CLKIN cycle (confirmed via phase math at our test frequency). In one capture, Channel A and B of the same device landed in different phase groups, suggesting the ambiguity is inside each channel's own SYNC-to-CLKIN synchronizer, not board/trace related.

1. What causes this is SYNC captured by an independent internal flip-flop (clocked from internal CLKIN) per channel, subject to normal metastability, similar to the divider-phase-ambiguity described in SBAA520?
2. What is the recommended fix is detecting the resulting whole-cycle offset once per boot and correcting it digitally (FPGA-side delay) the right approach, or does TI recommend something else for reliable multi-chip phase coherence with this device?

As discussed in the previous case, I am using the ADS5407 multi-device synchronization mechanism with SYNCIN and SYNCOUT, following the procedure described in the datasheet.

However, I am still unable to achieve fully deterministic synchronization between all of my ADS5407 devices.

I am using multiple ADS5407 ADCs with a common clock and synchronization mechanism. I provide the SYNCIN pulse to the ADCs and use the corresponding SYNCOUT signal at the FPGA to identify and align the ADC data streams.

During repeated testing with the same bitstream and same hardware configuration, I observed that the captured ADC data is sometimes shifted by approximately one ADC clock/sample relative to the other data streams. In other words, after reprogramming/testing the same bitstream, the relative alignment is not always deterministic, and I can observe a one-clock-cycle sample shift.

This is unexpected because I am following the SYNCIN/SYNCOUT synchronization mechanism as  described in the ADS5407 datasheet.

I also found the TI application note:

Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAs

and noticed that it discusses additional sources of synchronization variation, including the relationship between the ADC clock, synchronization signal, FPGA capture clock, and timestamp/data alignment.

Could you please help clarify the following points for the ADS5407 specifically?

1. Can the ADS5407 SYNCIN/SYNCOUT mechanism guarantee deterministic sample-level alignment after every power cycle or FPGA reprogramming?
2. If SYNCOUT is correctly detected in the FPGA, can there still be a one-sample/one-DCLK-cycle ambiguity in the captured data?
3. Is there any specific requirement on the phase relationship between SYNCIN and CLKIN that must be maintained to guarantee deterministic synchronization?
4. What is the recommended method for using SYNCOUT in the FPGA to guarantee that all ADC data FIFOs/read pointers start from exactly the same sample?
5. Should the FPGA capture clock also be phase-synchronized with the ADC clock/SYNC signal? If so, could you recommend the preferred implementation?
6. Is there any additional ADS5407 register configuration, clock phase adjustment, or synchronization procedure that should be performed before using SYNCIN/SYNCOUT?
7. Could the observed one-clock-cycle shift be related to the SYNCIN rising edge being captured on different clock edges/phases inside different ADS5407 devices?

I would appreciate your guidance on the recommended synchronization procedure for achieving deterministic sample alignment across all ADS5407 devices.

I can also provide the information if required

Thanks.

Regards,

Frank