Part Number: DAC39RF20EVM
Other Parts Discussed in Thread: DAC39RF20
I've just powered up a DAC39RF20 EVM and I'm following section 2.1.8 of the DAC39RF20 Eval Module Users guide, which walks us through connecting and turning on the boards. After I've set the chirp up and I've returned to the J59 Commander RF20 to "Setup FPGA", I see the error "**Expecting the PLL reference frequency to be 312.5 MHz", "**the PPL Selected is QPLL0". The console in J59 commander then reflects the error:
Here is a screen shot of the j59_server:
When I look at the clocking tab of DAC39RF20, I see 20 GHz for the FDAC and 1.25 GHz for the REF_CLK input. I'm providing 20 GHz, 6 dBm to DAC CLK p, and 1.25 GHz, 6 dBm to LMK CLK, and the 1.25 GHz signal generator is locked to the 20 GHz signal generator.
I have separate 12VDC supplies, with the TSW board drawing about 0.58 amps, EVM board drawing 0.794 amps.
There are two switches on the EVM not mentioned in the users guide or included in the pictures. One is PIN CTRL and is ON, the other is FPGA IO and is set to VADJ.
How can I get past this error and generate a chirp waveform?
Thanks,
Doug