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ADC3444: ADC3444 – Deterministic FCLK phase and sample alignment between two devices

grzegorz
Prodigy 30 points

Part Number: ADC3444
Other Parts Discussed in Thread: LMK04832,

We are designing an 8-channel acquisition system using two ADC3444 devices, both clocked at 125 MHz from an LMK04832.

Configuration:

  • Sampling rate: 125 MSPS

  • Input clock divider: divide-by-1

  • LVDS interface: 2-wire

  • Both ADCs receive phase-aligned 125 MHz clocks

  • Both devices share a common reset signal

  • Each ADC provides its own FCLK and DCLK to the FPGA

We require deterministic sample alignment between all eight channels after every power-up and reset, without analog calibration.

Could you please clarify:

  1. Is the phase of FCLK deterministic relative to the input sampling clock after every power-up and reset?

  2. Can two ADC3444 devices produce FCLK signals differing by one sampling-clock period (8 ns) even when their input clocks are phase-aligned?

  3. Does the specified ADC latency guarantee that sample N from both devices corresponds to the same sampling-clock cycle?

  4. Can SYSREF be used to guarantee deterministic FCLK alignment when the input clock divider is set to divide-by-1?

  5. Is there a recommended reset or initialization sequence that guarantees deterministic sample alignment between two ADC3444 devices without an external analog calibration signal?

Our goal is guaranteed sample-to-sample synchronization across all eight channels, including after repeated power cycling.

Thank you.
Grzegorz

  • 0
    TI__Prodigy 590 points

    Hi Grzegorz,

    To answer your questions directly:

    FCLK phase is not deterministic across power cycles without SYSREF. In 2-wire (7x) mode, FCLK = fs/2 (62.5 MHz at 125 MSPS), generated by an internal divider that can initialize to either of two phases after each reset. Two independently powered devices can have FCLK offset by exactly one full sampling-clock period (8 ns) - which means Device 1's "sample N" boundary aligns with Device 2's "sample N+1" boundary. The ADC latency specification does not resolve this; it is consistent within a device but does not constrain the FCLK framing phase.

    SYSREF is required even with the input clock divider set to divide-by-1. The input clock divider and the internal FCLK divider are separate. SYSREF per section 9.3.2.1 synchronizes the input clock divider, but the fs/2 FCLK stage has its own phase ambiguity that also needs SYSREF to resolve. Apply a single SYSREF pulse simultaneously to both devices after clocks are stable, meeting the setup/hold requirements from Table 7.13 (tSU = 1000 ps, tH = 100 ps, referenced to input clock falling edge).

    For your LMK04832 + dual ADC3444 system:
    1. Assert RESET to both devices simultaneously via a common line
    2. Issue SYSREF simultaneously to both SYSREF pins with matched PCB trace lengths
    3. Route FCLK from each device independently to the FPGA - do not assume they are phase-coincident (tDELAY variation per Table 7.14 adds up to 2.9 ns sub-cycle skew device-to-device)
    4. Use each device's own FCLK to capture its data,When operating at divide-by-1, the input clock divider is effectively bypassed, and SYSREF does not act on it.
    5. Validate with a test pattern (alternating or ramp) to confirm sample boundaries are aligned

    The 2.9 ns tDELAY variation is sub-cycle and will not cause sample-index misalignment, but the two FCLKs will not be coincident at the FPGA - independent routing is the correct approach.

    --Samba.

  • 0 in reply to Sambasiva Rao Kotha
    Prodigy 30 points

    Hi Samba,

    Thank you for your detailed response.

    Before finalizing our PCB design, I would like to clarify one important point concerning SYSREF and the internal FCLK divider.

    Section 9.3.2.1 and Figure 150 of the ADC3444 datasheet describe SYSREF synchronization of the input clock divider (÷2 or ÷4).

    However, you mentioned that SYSREF also resolves the phase ambiguity of the internal FCLK divider (fs/2), even when the input clock divider is bypassed (÷1).

    Could you please clarify the following:

    1. 125 MHz CLKIN, divider ÷1: Does a common SYSREF pulse explicitly synchronize the internal FCLK divider in both ADC3444 devices, guaranteeing deterministic sample-index alignment after every power-up?

    2. 250 MHz CLKIN, divider ÷2: Would this configuration provide a more reliable or better-documented synchronization mechanism? Does SYSREF synchronization of the input divider also guarantee deterministic alignment of the internal FCLK dividers?

    3. Which configuration would TI recommend for guaranteed sample-index alignment of two ADC3444 devices operating at 125 MSPS?

    4. Is a single SYSREF pulse sufficient after clocks are stable and both ADCs have been reset and configured? Are any specific register settings or timing sequences required?

    Our requirement is that sample N from all eight channels must correspond to the same sampling instant after every power-up, without analog calibration.

    We would appreciate an explicit confirmation of whether this requirement is guaranteed by the ADC3444 architecture.

    Thank you for your support.

    Grzegorz