ADS1217 problem

Jim,

Can you send me your schematic?  If you are measuring +/-1 volt, then 0V should be code 0.  If the AIN- input is at 1.25V, and your AIN+ input is connected to the input circuit that is offset by 1.25V, the input should be 0V differential and the resultant code should be around or near zero (within the region of noise.)  It appears that you have considerable offset.

Which filter option are you using?  How are you deriving your reference/offset?  If you are using the internal reference, do you have a cap on the Vrcap pin?  How are you verifying the accuracy of your measurement?

Best regards,

Bob B

Bob

I can’t send the schematic but I can clear up my description
of the ADC input circuit

The ADC input is used in a unipolar mode. Plus input is channel
2, signal from an instrumentation amp, Minus input is channel 3 and is tied to
ground. To accommodate +/- 1 volt from the outside world the input circuit adds
a 1.25 volt offset so the ADC sees a voltage swing of .25 volts to 2.25 volts. The
ADC internal reference is at 1.25 V.  Zero
volts in becomes 1.25 volts or about 1/2 scale at the ADC.  The analog offset is derived from the ADC
internal reference. Vrcap  .001 uf  is in place.

I am using system calibration, establishing an offset and
gain in firmware that is applied to ADC counts.

This works well almost all the time. Problem is occasionally
the ADC count shifts by what looks like 65000 counts for a single sample.
Hundreds of samples before and after this error are fine.  It appears that the most significant byte of
the count changes by +/- 1 bit.

Filter is Sinc3

I am doing a single read (command = 1) 5 time / second. There is a 2 ms delay between clocking in the read command and clocking
out data.

Thanks

Jim

Bob

I should also mention that this only happens at specific input voltages. With 0 V in (1.25 at ADC) the ADC result is around 0x7c0000. If I change the input by 0.1 mV the problem goes away. If I move the input to .008 V the problem comes back. With our current calibration the 8 mV is about 65000 counts or 16 bits

Thanks

Jim,

Ok, I misunderstood your configuration.  Can you send me all of your register settings?  You might be seeing an idle tone or an aliased signal.  Do you have any anti-alias filtering at the input?  Have you tried altering the decimation ratio?

Best regards,

Bob B

Bob,

Register settings are:

Reg 0 = 0x8 ->  Fmod=Fosc/128, Internal ref on @ 1.25

Reg 1 = 0x23

Reg 2 = 0 -> PGA gain = 1, IDACs off, BOCS off

Reg 3 = 0 IDCA1

Reg 4 = 0 IDAC2

Reg 5 = 0x17 -> Offset DAC set by firmware

Reg 6 = 0 Digital IO output value

Reg 7 = 0xff Digital IO direction -0xff = all inputs

Reg 8 = 0x80 -> Decimation register 8 LSBs

Reg 9 = 0xF2 -> Unipolar, Sinc3 fiter, Decimation register 3 MSBs ->DR = 640 decimal -> 60 sps

Reg a = 0 Default calibration offset

Reg b = 0 Default calibration offset

Reg c = 0 Default calibration offset

Reg d = 0x24 Default full scale adjust

Reg e = 0x90 Default full scale adjust

Reg f = 0x67 Default full scale adjust

We do not have an anti-alias filter, input is DC except for noise. I have not tried another decimation value.

What is an idle tone?

Thanks

Jim

Bob,

More info.

Most times I see a single isolated error sample. I have seen a few cases where 2 or 3 consecutive samples have errors.

Consecutive errors alternate between +65000 and -65000. The order may change but if one sample error is plus the next is minus?

Jim 

Jim,

Idle tones are a result of interactions in the modulator and digital filter.  These can be result of specific combinations of ones and zeros output by the modulator and where the transition states take place.  The stability of the reference is important here too.

Aliasing will always take place related to the sampling frequency and any noise frequencies that pass through the wide bandwidth of the INA.  These frequencies will fold back into the passband.  Even when reading a DC input it is a good idea to limit the input frequencies.  Adding a RC, or at least a C or about 10nF across the inputs is a good idea.

If some of the reading are correct then go bad, this is sounding more like a bit shift in the communication.  This can be caused by noise spikes on the SCLK line.

Best regards,

Bob B

Bob, 

Could this be a data read sync problem.

I am doing a single read but do not have access to the DRDY line. Only access is via serial port. Is it possible to get and error like this if the read happens while DRDY is high?

I tried the following: 1. Send a DSYNC command, 2. Read register 9 until DRDY bit is low, 3. Send a READ DATA command.

My understanding is that the DSYNC resets the modulator and forces DRDY high. When DRDY goes low data is ready to read. This seems to help.

Will there be any side effects?  

Thanks

Jim

Thanks Bob,

I checked DRDY and it stays high for 50+ ms. With my Fdata rate of 60 Hz, DRDY looks like it is high for the 3 samples of Sinc3 and data looks good..

One more question.

I found if I do a single read, wait for DRDY low, then do a second single read - data looks good. This is faster than isssuing a DSYNC and waiting for the third sample.

Is this a valid way to effect sync via the serial port?

Thanks again

Jim

Morning Bob,

Thanks for the help on my data read sync problem. 

I have a question on a different ADS1217 issue.

From the data sheet I expect my the ADS1217 input voltage to be limited +/- 2*Vref. My application is uni-polar and ties the negative input to ground. With that I expect the input range to be 0 to 2*Vref.

Using an internal refference of 1.25 volts I would expect the output to saturate with a 2.5 V input. But its doesn't. I can run up to 3.2V.

I assume the 2*Vref limit would be in the modulator and not depend on the digital filter / decimation ratio or calibration registers?

What am I missing?

Thanks

Jim

Jim,

The full scale range is +/- 2 VREF/PGA for bipolar and 4VREF/PGA for unipolar.  See Table V and the discussion on page 25 of the datasheet.

Best regards,

Bob B