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ADC12D1600RF

Dennis Meneely
Prodigy 30 points

Other Parts Discussed in Thread: ADC12D1600RF

I cannot find any timing diagrams for non DES and DDR mode together.  Can you verify the ADC12D1600RF can be setup as listed below:

Non DES - non Dual Edge Sampling and

4/3 GHz input clock sample rate and

Demux mode - data at half the sample rate on two busses and

DDR mode - Double Data Rate on each bus and

ECM mode - extended control mode and

One channel powered down.

 

Thanks

Dennis Meneely

DMeneely@drs-ds.com

  • 0
    TI__Mastermind 44680 points

    Hi Dennis

    Figure 4 on page 32 (current web datasheet) shows output data clocking for 1:2 demux. You can see that the data outputs update on both edges of DCLK, so this is the DDR mode.

    Your desired mode of operation is definitely possible, and is pretty standard. The I or Q channel can be powered down using either the PDI/Q bits in Configuration Register 1, or the PDI and PDQ control pins, see Section 17.3.4.  Also please see TABLE 25 on how to terminate the analog inputs of a channel that is powered down.

    I hope this is helpful. Please let us know if you need anything else.

    Best regards,

    Jim B